mirror of https://gitee.com/openkylin/linux.git
drm/i915: use intel_uncore for all forcewake get/put
Now that the internal code all works on intel_uncore, flip the external-facing interface. v2: fix GVT. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-4-daniele.ceraolospurio@intel.com
This commit is contained in:
Daniele Ceraolo Spurio
Chris Wilson
parent
f568eeee53
commit
3ceea6a1b4
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@ -356,7 +356,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
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if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9)
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fw |= FORCEWAKE_RENDER;
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intel_uncore_forcewake_get(dev_priv, fw);
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intel_uncore_forcewake_get(&dev_priv->uncore, fw);
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I915_WRITE_FW(reg, 0x1);
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@ -365,7 +365,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
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else
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vgpu_vreg_t(vgpu, reg) = 0;
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intel_uncore_forcewake_put(dev_priv, fw);
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intel_uncore_forcewake_put(&dev_priv->uncore, fw);
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gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
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}
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@ -552,9 +552,9 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
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* performace for batch mmio read/write, so we need
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* handle forcewake mannually.
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*/
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
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switch_mmio(pre, next, ring_id);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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}
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/**
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@ -988,7 +988,7 @@ static int workload_thread(void *priv)
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workload->ring_id, workload);
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if (need_force_wake)
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intel_uncore_forcewake_get(gvt->dev_priv,
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intel_uncore_forcewake_get(&gvt->dev_priv->uncore,
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FORCEWAKE_ALL);
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ret = dispatch_workload(workload);
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@ -1010,7 +1010,7 @@ static int workload_thread(void *priv)
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complete_current_workload(gvt, ring_id);
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if (need_force_wake)
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intel_uncore_forcewake_put(gvt->dev_priv,
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intel_uncore_forcewake_put(&gvt->dev_priv->uncore,
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FORCEWAKE_ALL);
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intel_runtime_pm_put_unchecked(gvt->dev_priv);
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@ -1094,7 +1094,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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}
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/* RPSTAT1 is in the GT power well */
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
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reqf = I915_READ(GEN6_RPNSWREQ);
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if (INTEL_GEN(dev_priv) >= 9)
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@ -1122,7 +1122,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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cagf = intel_gpu_freq(dev_priv,
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intel_get_cagf(dev_priv, rpstat));
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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if (INTEL_GEN(dev_priv) >= 11) {
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pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
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@ -2060,12 +2060,12 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
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u32 rpup, rpupei;
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u32 rpdown, rpdownei;
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
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rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
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rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
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rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
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rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
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rps_power_to_str(rps->power.mode));
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@ -4251,7 +4251,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
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return 0;
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file->private_data = (void *)(uintptr_t)intel_runtime_pm_get(i915);
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intel_uncore_forcewake_user_get(i915);
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intel_uncore_forcewake_user_get(&i915->uncore);
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return 0;
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}
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@ -4263,7 +4263,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file)
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if (INTEL_GEN(i915) < 6)
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return 0;
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intel_uncore_forcewake_user_put(i915);
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intel_uncore_forcewake_user_put(&i915->uncore);
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intel_runtime_pm_put(i915,
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(intel_wakeref_t)(uintptr_t)file->private_data);
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@ -4318,7 +4318,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
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GEM_TRACE("\n");
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wakeref = intel_runtime_pm_get(i915);
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intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
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intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
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/*
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* As we have just resumed the machine and woken the device up from
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@ -4339,7 +4339,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
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*/
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intel_engines_sanitize(i915, false);
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intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
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intel_runtime_pm_put(i915, wakeref);
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mutex_lock(&i915->drm.struct_mutex);
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@ -4438,7 +4438,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
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WARN_ON(i915->gt.awake);
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mutex_lock(&i915->drm.struct_mutex);
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intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
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intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
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i915_gem_restore_gtt_mappings(i915);
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i915_gem_restore_fences(i915);
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@ -4460,7 +4460,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
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goto err_wedged;
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out_unlock:
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intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
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mutex_unlock(&i915->drm.struct_mutex);
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return;
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@ -4549,7 +4549,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
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dev_priv->gt.last_init_time = ktime_get();
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/* Double layer security blanket, see i915_gem_init() */
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
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if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
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I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
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@ -4604,14 +4604,14 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
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if (ret)
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goto cleanup_uc;
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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return 0;
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cleanup_uc:
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intel_uc_fini_hw(dev_priv);
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out:
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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return ret;
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}
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@ -4815,7 +4815,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
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* just magically go away.
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*/
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mutex_lock(&dev_priv->drm.struct_mutex);
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
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ret = i915_gem_init_ggtt(dev_priv);
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if (ret) {
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@ -4877,7 +4877,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
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goto err_init_hw;
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}
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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return 0;
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@ -4912,7 +4912,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
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i915_gem_fini_scratch(dev_priv);
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err_ggtt:
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err_unlock:
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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err_uc_misc:
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@ -1364,7 +1364,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
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free_oa_buffer(dev_priv);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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intel_runtime_pm_put(dev_priv, stream->wakeref);
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if (stream->ctx)
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@ -2093,7 +2093,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
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* references will effectively disable RC6.
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*/
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stream->wakeref = intel_runtime_pm_get(dev_priv);
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
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ret = alloc_oa_buffer(dev_priv);
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if (ret)
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@ -2127,7 +2127,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
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err_oa_buf_alloc:
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put_oa_config(dev_priv, stream->oa_config);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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intel_runtime_pm_put(dev_priv, stream->wakeref);
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err_config:
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@ -569,7 +569,7 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask)
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* If the power well sleeps during the reset, the reset
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* request may be dropped and never completes (causing -EIO).
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*/
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intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
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intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
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for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
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/*
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* We stop engines, otherwise we might get failed reset and a
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@ -593,7 +593,7 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask)
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ret = reset(i915, engine_mask, retry);
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preempt_enable();
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}
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intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
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return ret;
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}
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@ -622,9 +622,9 @@ int intel_reset_guc(struct drm_i915_private *i915)
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GEM_BUG_ON(!HAS_GUC(i915));
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intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
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intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
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ret = gen6_hw_domain_reset(i915, guc_domain);
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intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
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return ret;
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}
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@ -642,7 +642,7 @@ static void reset_prepare_engine(struct intel_engine_cs *engine)
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* written to the powercontext is undefined and so we may lose
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* GPU state upon resume, i.e. fail to restart after a reset.
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*/
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intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL);
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intel_uncore_forcewake_get(&engine->i915->uncore, FORCEWAKE_ALL);
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engine->reset.prepare(engine);
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}
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@ -713,7 +713,7 @@ static int gt_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
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static void reset_finish_engine(struct intel_engine_cs *engine)
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{
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engine->reset.finish(engine);
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intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&engine->i915->uncore, FORCEWAKE_ALL);
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}
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struct i915_gpu_restart {
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@ -9519,7 +9519,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
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* Make sure we're not on PC8 state before disabling PC8, otherwise
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* we'll hang the machine. To prevent PC8 state, just enable force_wake.
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*/
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
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if (val & LCPLL_POWER_DOWN_ALLOW) {
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val &= ~LCPLL_POWER_DOWN_ALLOW;
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@ -9551,7 +9551,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
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DRM_ERROR("Switching back to LCPLL failed\n");
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}
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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intel_update_cdclk(dev_priv);
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intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
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@ -919,7 +919,7 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
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FW_REG_READ | FW_REG_WRITE);
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spin_lock_irq(&dev_priv->uncore.lock);
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intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
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intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw_domains);
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mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
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@ -937,7 +937,7 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
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I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
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intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
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intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw_domains);
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spin_unlock_irq(&dev_priv->uncore.lock);
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return ret;
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@ -369,14 +369,14 @@ void intel_guc_init_params(struct intel_guc *guc)
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* they are power context saved so it's ok to release forcewake
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* when we are done here and take it again at xfer time.
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*/
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
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intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_BLITTER);
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I915_WRITE(SOFT_SCRATCH(0), 0);
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for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
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I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_BLITTER);
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}
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int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
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@ -414,7 +414,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
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*action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
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mutex_lock(&guc->send_mutex);
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intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
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intel_uncore_forcewake_get(&dev_priv->uncore, guc->send_regs.fw_domains);
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for (i = 0; i < len; i++)
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I915_WRITE(guc_send_reg(guc, i), action[i]);
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@ -454,7 +454,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
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ret = INTEL_GUC_MSG_TO_DATA(status);
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out:
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intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
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intel_uncore_forcewake_put(&dev_priv->uncore, guc->send_regs.fw_domains);
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mutex_unlock(&guc->send_mutex);
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return ret;
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@ -241,7 +241,7 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
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GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
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|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
guc_prepare_xfer(guc);
|
||||
|
||||
|
|
@ -254,7 +254,7 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
|
|||
|
||||
ret = guc_xfer_ucode(guc, vma);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
|
|||
|
||||
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
|
||||
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
/* Set the source address for the uCode */
|
||||
offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
|
||||
|
|
@ -140,7 +140,7 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
|
|||
/* Disable the bits once DMA is over */
|
||||
I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6781,9 +6781,9 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
|
|||
* punit into committing the voltage change) as that takes a lot less
|
||||
* power than the render powerwell.
|
||||
*/
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_MEDIA);
|
||||
err = valleyview_set_rps(dev_priv, val);
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_MEDIA);
|
||||
|
||||
if (err)
|
||||
DRM_ERROR("Failed to set RPS for idle\n");
|
||||
|
|
@ -6933,11 +6933,11 @@ static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
|
|||
{
|
||||
/* We're doing forcewake before Disabling RC6,
|
||||
* This what the BIOS expects when going into suspend */
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
I915_WRITE(GEN6_RC_CONTROL, 0);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
|
||||
|
|
@ -7096,7 +7096,7 @@ static void reset_rps(struct drm_i915_private *dev_priv,
|
|||
/* See the Gen9_GT_PM_Programming_Guide doc for the below */
|
||||
static void gen9_enable_rps(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
/* Program defaults and thresholds for RPS */
|
||||
if (IS_GEN(dev_priv, 9))
|
||||
|
|
@ -7114,7 +7114,7 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
|
|||
* RP_INTERRUPT_LIMITS & RPNSWREQ registers */
|
||||
reset_rps(dev_priv, gen6_set_rps);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
|
||||
|
|
@ -7128,7 +7128,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
|
|||
|
||||
/* 1b: Get forcewake during program sequence. Although the driver
|
||||
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
/* 2a: Disable RC states. */
|
||||
I915_WRITE(GEN6_RC_CONTROL, 0);
|
||||
|
|
@ -7205,7 +7205,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
|
|||
I915_WRITE(GEN9_PG_ENABLE,
|
||||
GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
|
||||
|
|
@ -7218,7 +7218,7 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
|
|||
|
||||
/* 1b: Get forcewake during program sequence. Although the driver
|
||||
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
/* 2a: Disable RC states. */
|
||||
I915_WRITE(GEN6_RC_CONTROL, 0);
|
||||
|
|
@ -7239,14 +7239,14 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
|
|||
GEN7_RC_CTL_TO_MODE |
|
||||
GEN6_RC_CTL_RC6_ENABLE);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
static void gen8_enable_rps(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_rps *rps = &dev_priv->gt_pm.rps;
|
||||
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
/* 1 Program defaults and thresholds for RPS*/
|
||||
I915_WRITE(GEN6_RPNSWREQ,
|
||||
|
|
@ -7279,7 +7279,7 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
|
|||
|
||||
reset_rps(dev_priv, gen6_set_rps);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
|
||||
|
|
@ -7299,7 +7299,7 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
|
|||
I915_WRITE(GTFIFODBG, gtfifodbg);
|
||||
}
|
||||
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
/* disable the counters and set deterministic thresholds */
|
||||
I915_WRITE(GEN6_RC_CONTROL, 0);
|
||||
|
|
@ -7347,7 +7347,7 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
|
|||
DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
|
||||
}
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
static void gen6_enable_rps(struct drm_i915_private *dev_priv)
|
||||
|
|
@ -7358,7 +7358,7 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
|
|||
* Perhaps there might be some value in exposing these to
|
||||
* userspace...
|
||||
*/
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
/* Power down if completely idle for over 50ms */
|
||||
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
|
||||
|
|
@ -7366,7 +7366,7 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
|
|||
|
||||
reset_rps(dev_priv, gen6_set_rps);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
|
||||
|
|
@ -7789,7 +7789,7 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
|
|||
|
||||
/* 1a & 1b: Get forcewake during program sequence. Although the driver
|
||||
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
/* Disable RC states. */
|
||||
I915_WRITE(GEN6_RC_CONTROL, 0);
|
||||
|
|
@ -7821,14 +7821,14 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
|
|||
rc6_mode = GEN7_RC_CTL_TO_MODE;
|
||||
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
/* 1: Program defaults and thresholds for RPS*/
|
||||
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
|
||||
|
|
@ -7863,7 +7863,7 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
|
|||
|
||||
reset_rps(dev_priv, valleyview_set_rps);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
|
||||
|
|
@ -7881,7 +7881,7 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
|
|||
I915_WRITE(GTFIFODBG, gtfifodbg);
|
||||
}
|
||||
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
/* Disable RC states. */
|
||||
I915_WRITE(GEN6_RC_CONTROL, 0);
|
||||
|
|
@ -7906,14 +7906,14 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
|
|||
I915_WRITE(GEN6_RC_CONTROL,
|
||||
GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
|
||||
I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
|
||||
|
|
@ -7947,7 +7947,7 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
|
|||
|
||||
reset_rps(dev_priv, valleyview_set_rps);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
static unsigned long intel_pxfreq(u32 vidfreq)
|
||||
|
|
@ -9999,7 +9999,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
|
|||
fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
|
||||
|
||||
spin_lock_irqsave(&dev_priv->uncore.lock, flags);
|
||||
intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
|
||||
intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw_domains);
|
||||
|
||||
/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
|
||||
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
||||
|
|
@ -10040,7 +10040,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
|
|||
time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
|
||||
dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
|
||||
|
||||
intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
|
||||
intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw_domains);
|
||||
spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
|
||||
|
||||
return mul_u64_u32_div(time_hw, mul, div);
|
||||
|
|
|
|||
|
|
@ -640,7 +640,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
|
|||
struct intel_ring *ring = engine->buffer;
|
||||
int ret = 0;
|
||||
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
if (!stop_ring(engine)) {
|
||||
/* G45 ring initialization often fails to reset head to zero */
|
||||
|
|
@ -727,7 +727,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
|
|||
/* Papering over lost _interrupts_ immediately following the restart */
|
||||
intel_engine_queue_breadcrumbs(engine);
|
||||
out:
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -2075,7 +2075,7 @@ static void gen6_bsd_submit_request(struct i915_request *request)
|
|||
{
|
||||
struct drm_i915_private *dev_priv = request->i915;
|
||||
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
/* Every tail move must follow the sequence below */
|
||||
|
||||
|
|
@ -2105,7 +2105,7 @@ static void gen6_bsd_submit_request(struct i915_request *request)
|
|||
I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
|
||||
_MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
static int mi_flush_dw(struct i915_request *rq, u32 flags)
|
||||
|
|
|
|||
|
|
@ -610,7 +610,7 @@ static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
|
|||
|
||||
/**
|
||||
* intel_uncore_forcewake_get - grab forcewake domain references
|
||||
* @dev_priv: i915 device instance
|
||||
* @uncore: the intel_uncore structure
|
||||
* @fw_domains: forcewake domains to get reference on
|
||||
*
|
||||
* This function can be used get GT's forcewake domain references.
|
||||
|
|
@ -621,16 +621,15 @@ static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
|
|||
* call to intel_unforce_forcewake_put(). Usually caller wants all the domains
|
||||
* to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
|
||||
*/
|
||||
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
|
||||
void intel_uncore_forcewake_get(struct intel_uncore *uncore,
|
||||
enum forcewake_domains fw_domains)
|
||||
{
|
||||
struct intel_uncore *uncore = &dev_priv->uncore;
|
||||
unsigned long irqflags;
|
||||
|
||||
if (!uncore->funcs.force_wake_get)
|
||||
return;
|
||||
|
||||
assert_rpm_wakelock_held(dev_priv);
|
||||
assert_rpm_wakelock_held(uncore_to_i915(uncore));
|
||||
|
||||
spin_lock_irqsave(&uncore->lock, irqflags);
|
||||
__intel_uncore_forcewake_get(uncore, fw_domains);
|
||||
|
|
@ -639,19 +638,17 @@ void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
|
|||
|
||||
/**
|
||||
* intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
|
||||
* @dev_priv: i915 device instance
|
||||
* @uncore: the intel_uncore structure
|
||||
*
|
||||
* This function is a wrapper around intel_uncore_forcewake_get() to acquire
|
||||
* the GT powerwell and in the process disable our debugging for the
|
||||
* duration of userspace's bypass.
|
||||
*/
|
||||
void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
|
||||
void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
|
||||
{
|
||||
struct intel_uncore *uncore = &dev_priv->uncore;
|
||||
|
||||
spin_lock_irq(&uncore->lock);
|
||||
if (!uncore->user_forcewake.count++) {
|
||||
intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
|
||||
|
||||
/* Save and disable mmio debugging for the user bypass */
|
||||
uncore->user_forcewake.saved_mmio_check =
|
||||
|
|
@ -667,19 +664,19 @@ void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
|
|||
|
||||
/**
|
||||
* intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
|
||||
* @dev_priv: i915 device instance
|
||||
* @uncore: the intel_uncore structure
|
||||
*
|
||||
* This function complements intel_uncore_forcewake_user_get() and releases
|
||||
* the GT powerwell taken on behalf of the userspace bypass.
|
||||
*/
|
||||
void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
|
||||
void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
|
||||
{
|
||||
struct intel_uncore *uncore = &dev_priv->uncore;
|
||||
struct drm_i915_private *i915 = uncore_to_i915(uncore);
|
||||
|
||||
spin_lock_irq(&uncore->lock);
|
||||
if (!--uncore->user_forcewake.count) {
|
||||
if (intel_uncore_unclaimed_mmio(dev_priv))
|
||||
dev_info(dev_priv->drm.dev,
|
||||
if (intel_uncore_unclaimed_mmio(i915))
|
||||
dev_info(i915->drm.dev,
|
||||
"Invalid mmio detected during user access\n");
|
||||
|
||||
uncore->unclaimed_mmio_check =
|
||||
|
|
@ -687,24 +684,22 @@ void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
|
|||
i915_modparams.mmio_debug =
|
||||
uncore->user_forcewake.saved_mmio_debug;
|
||||
|
||||
intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
|
||||
}
|
||||
spin_unlock_irq(&uncore->lock);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_uncore_forcewake_get__locked - grab forcewake domain references
|
||||
* @dev_priv: i915 device instance
|
||||
* @uncore: the intel_uncore structure
|
||||
* @fw_domains: forcewake domains to get reference on
|
||||
*
|
||||
* See intel_uncore_forcewake_get(). This variant places the onus
|
||||
* on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
|
||||
*/
|
||||
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
|
||||
void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
|
||||
enum forcewake_domains fw_domains)
|
||||
{
|
||||
struct intel_uncore *uncore = &dev_priv->uncore;
|
||||
|
||||
lockdep_assert_held(&uncore->lock);
|
||||
|
||||
if (!uncore->funcs.force_wake_get)
|
||||
|
|
@ -736,16 +731,15 @@ static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
|
|||
|
||||
/**
|
||||
* intel_uncore_forcewake_put - release a forcewake domain reference
|
||||
* @dev_priv: i915 device instance
|
||||
* @uncore: the intel_uncore structure
|
||||
* @fw_domains: forcewake domains to put references
|
||||
*
|
||||
* This function drops the device-level forcewakes for specified
|
||||
* domains obtained by intel_uncore_forcewake_get().
|
||||
*/
|
||||
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
|
||||
void intel_uncore_forcewake_put(struct intel_uncore *uncore,
|
||||
enum forcewake_domains fw_domains)
|
||||
{
|
||||
struct intel_uncore *uncore = &dev_priv->uncore;
|
||||
unsigned long irqflags;
|
||||
|
||||
if (!uncore->funcs.force_wake_put)
|
||||
|
|
@ -758,17 +752,15 @@ void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
|
|||
|
||||
/**
|
||||
* intel_uncore_forcewake_put__locked - grab forcewake domain references
|
||||
* @dev_priv: i915 device instance
|
||||
* @uncore: the intel_uncore structure
|
||||
* @fw_domains: forcewake domains to get reference on
|
||||
*
|
||||
* See intel_uncore_forcewake_put(). This variant places the onus
|
||||
* on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
|
||||
*/
|
||||
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
|
||||
void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
|
||||
enum forcewake_domains fw_domains)
|
||||
{
|
||||
struct intel_uncore *uncore = &dev_priv->uncore;
|
||||
|
||||
lockdep_assert_held(&uncore->lock);
|
||||
|
||||
if (!uncore->funcs.force_wake_put)
|
||||
|
|
@ -1535,11 +1527,11 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
|
|||
* the access.
|
||||
*/
|
||||
disable_rpm_wakeref_asserts(dev_priv);
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
enable_rpm_wakeref_asserts(dev_priv);
|
||||
break;
|
||||
case MBI_PMIC_BUS_ACCESS_END:
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1796,13 +1788,13 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
|
|||
might_sleep_if(slow_timeout_ms);
|
||||
|
||||
spin_lock_irq(&dev_priv->uncore.lock);
|
||||
intel_uncore_forcewake_get__locked(dev_priv, fw);
|
||||
intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
|
||||
|
||||
ret = __intel_wait_for_register_fw(dev_priv,
|
||||
reg, mask, value,
|
||||
fast_timeout_us, 0, ®_value);
|
||||
|
||||
intel_uncore_forcewake_put__locked(dev_priv, fw);
|
||||
intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw);
|
||||
spin_unlock_irq(&dev_priv->uncore.lock);
|
||||
|
||||
if (ret && slow_timeout_ms)
|
||||
|
|
|
|||
|
|
@ -163,20 +163,20 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
|
|||
#define FW_REG_READ (1)
|
||||
#define FW_REG_WRITE (2)
|
||||
|
||||
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
|
||||
void intel_uncore_forcewake_get(struct intel_uncore *uncore,
|
||||
enum forcewake_domains domains);
|
||||
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
|
||||
void intel_uncore_forcewake_put(struct intel_uncore *uncore,
|
||||
enum forcewake_domains domains);
|
||||
/* Like above but the caller must manage the uncore.lock itself.
|
||||
* Must be used with I915_READ_FW and friends.
|
||||
*/
|
||||
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
|
||||
void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
|
||||
enum forcewake_domains domains);
|
||||
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
|
||||
void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
|
||||
enum forcewake_domains domains);
|
||||
|
||||
void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv);
|
||||
void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv);
|
||||
void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
|
||||
void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
|
||||
|
||||
int __intel_wait_for_register(struct drm_i915_private *dev_priv,
|
||||
i915_reg_t reg,
|
||||
|
|
|
|||
|
|
@ -927,7 +927,7 @@ wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
|
|||
fw = wal_get_fw_for_rmw(dev_priv, wal);
|
||||
|
||||
spin_lock_irqsave(&dev_priv->uncore.lock, flags);
|
||||
intel_uncore_forcewake_get__locked(dev_priv, fw);
|
||||
intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
|
||||
|
||||
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
|
||||
u32 val = I915_READ_FW(wa->reg);
|
||||
|
|
@ -938,7 +938,7 @@ wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
|
|||
I915_WRITE_FW(wa->reg, val);
|
||||
}
|
||||
|
||||
intel_uncore_forcewake_put__locked(dev_priv, fw);
|
||||
intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw);
|
||||
spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -199,9 +199,9 @@ static int live_forcewake_ops(void *arg)
|
|||
goto out_rpm;
|
||||
}
|
||||
|
||||
intel_uncore_forcewake_get(i915, fw_domains);
|
||||
intel_uncore_forcewake_get(uncore, fw_domains);
|
||||
val = readl(reg);
|
||||
intel_uncore_forcewake_put(i915, fw_domains);
|
||||
intel_uncore_forcewake_put(uncore, fw_domains);
|
||||
|
||||
/* Flush the forcewake release (delayed onto a timer) */
|
||||
for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
|
||||
|
|
@ -263,7 +263,7 @@ static int live_forcewake_domains(void *arg)
|
|||
if (!valid)
|
||||
return -ENOMEM;
|
||||
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
check_for_unclaimed_mmio(dev_priv);
|
||||
for (offset = 0; offset < FW_RANGE; offset += 4) {
|
||||
|
|
@ -274,7 +274,7 @@ static int live_forcewake_domains(void *arg)
|
|||
set_bit(offset, valid);
|
||||
}
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
||||
|
||||
err = 0;
|
||||
for_each_set_bit(offset, valid, FW_RANGE) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue