mirror of https://gitee.com/openkylin/linux.git
drm/i915/ddi: switch to kernel types
Mixed C99 and kernel types use is getting ugly. Prefer kernel types. sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g' Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190118120125.15484-4-jani.nikula@intel.com
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@ -974,7 +974,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
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DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
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}
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static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
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static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
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{
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switch (pll->info->id) {
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case DPLL_ID_WRPLL1:
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@ -995,7 +995,7 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
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}
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}
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static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
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static u32 icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
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@ -1243,8 +1243,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
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enum intel_dpll_id pll_id)
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{
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i915_reg_t cfgcr1_reg, cfgcr2_reg;
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uint32_t cfgcr1_val, cfgcr2_val;
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uint32_t p0, p1, p2, dco_freq;
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u32 cfgcr1_val, cfgcr2_val;
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u32 p0, p1, p2, dco_freq;
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cfgcr1_reg = DPLL_CFGCR1(pll_id);
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cfgcr2_reg = DPLL_CFGCR2(pll_id);
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@ -1305,8 +1305,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
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int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
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enum intel_dpll_id pll_id)
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{
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uint32_t cfgcr0, cfgcr1;
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uint32_t p0, p1, p2, dco_freq, ref_clock;
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u32 cfgcr0, cfgcr1;
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u32 p0, p1, p2, dco_freq, ref_clock;
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if (INTEL_GEN(dev_priv) >= 11) {
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cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
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@ -1471,7 +1471,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum port port = encoder->port;
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int link_clock = 0;
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uint32_t pll_id;
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u32 pll_id;
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pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
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if (intel_port_is_combophy(dev_priv, port)) {
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@ -1496,7 +1496,7 @@ static void cnl_ddi_clock_get(struct intel_encoder *encoder,
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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int link_clock = 0;
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uint32_t cfgcr0;
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u32 cfgcr0;
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enum intel_dpll_id pll_id;
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pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
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@ -1550,7 +1550,7 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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int link_clock = 0;
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uint32_t dpll_ctl1;
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u32 dpll_ctl1;
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enum intel_dpll_id pll_id;
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pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
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@ -1739,7 +1739,7 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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uint32_t temp;
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u32 temp;
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temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
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if (state == true)
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@ -1757,7 +1757,7 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
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enum pipe pipe = crtc->pipe;
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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enum port port = encoder->port;
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uint32_t temp;
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u32 temp;
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/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
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temp = TRANS_DDI_FUNC_ENABLE;
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@ -1841,7 +1841,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
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uint32_t val = I915_READ(reg);
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u32 val = I915_READ(reg);
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val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
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val |= TRANS_DDI_PORT_NONE;
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@ -1863,7 +1863,7 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
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intel_wakeref_t wakeref;
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enum pipe pipe = 0;
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int ret = 0;
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uint32_t tmp;
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u32 tmp;
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wakeref = intel_display_power_get_if_enabled(dev_priv,
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intel_encoder->power_domain);
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@ -1896,7 +1896,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
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enum transcoder cpu_transcoder;
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intel_wakeref_t wakeref;
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enum pipe pipe = 0;
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uint32_t tmp;
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u32 tmp;
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bool ret;
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wakeref = intel_display_power_get_if_enabled(dev_priv,
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@ -2132,7 +2132,7 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
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}
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static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
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enum port port, uint8_t iboost)
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enum port port, u8 iboost)
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{
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u32 tmp;
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@ -2151,7 +2151,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
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struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum port port = encoder->port;
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uint8_t iboost;
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u8 iboost;
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if (type == INTEL_OUTPUT_HDMI)
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iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
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@ -2665,7 +2665,7 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
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icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
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}
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static uint32_t translate_signal_level(int signal_levels)
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static u32 translate_signal_level(int signal_levels)
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{
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int i;
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@ -2680,9 +2680,9 @@ static uint32_t translate_signal_level(int signal_levels)
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return 0;
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}
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static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
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static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
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{
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uint8_t train_set = intel_dp->train_set[0];
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u8 train_set = intel_dp->train_set[0];
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int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
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DP_TRAIN_PRE_EMPHASIS_MASK);
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@ -2707,7 +2707,7 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
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return 0;
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}
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uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
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u32 ddi_signal_levels(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
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struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
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@ -2721,7 +2721,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
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}
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static inline
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uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
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u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
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enum port port)
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{
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if (intel_port_is_combophy(dev_priv, port)) {
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@ -2857,7 +2857,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum port port = encoder->port;
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uint32_t val;
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u32 val;
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const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
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if (WARN_ON(!pll))
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@ -3356,7 +3356,7 @@ void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
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const struct drm_connector_state *old_conn_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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uint32_t val;
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u32 val;
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/*
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* Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
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@ -3644,7 +3644,7 @@ void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
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struct drm_i915_private *dev_priv =
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to_i915(intel_dig_port->base.base.dev);
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enum port port = intel_dig_port->base.port;
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uint32_t val;
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u32 val;
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bool wait = false;
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if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
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