First round of amlogic clock fixes for v5.4.

This fixes the clock rate propagation for the g12a cpu clocks and
 the gxbb adc clock.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAl2cMrUACgkQ5vwPHDfy
 2oW58g/+MG2D0vayigtblMRp2+wW6Lk2wmjTqqwdhS0pcw9Z3KG395hP3iMAI3fP
 K4Z5VpSHKumz0/Z/4W8cRwN/W4nrnVr1fm7GJUL19CdmfEFYUtkc3eAdZ4RcXohF
 y8tTMZ+kb5vgHb6xDCUD4GR6GOH9X5YHSIrAj4UCfW4XSRttXYopoyAuTVYhPChG
 cmW1fykWwriqgze+oaluXRaoFPgxViucYU2FWgTQD7Lrfftc0KKKoAhiv2XW3cUC
 9E9c5FOmA/XP0LXx9t8WtnoG5nO8l6oI/J90SsbyeBeyALxjJHTifAIi67Qjqei/
 tb+br6rbK8kWypU6rLBu60UNjbGZhKHpOE+gbYM8NHElgi5fLpa+2fNBfgOz8tuf
 Fqiz/f0lKjceVFz18XJFjfJSBjW6VLa6MaOOM63kkcWmd4jMSmvyhKxrgA0xMRlT
 +HY5pu/6YWXlNjK6kMI5FREti+JJbUZamJtf+YIu1Jg6KFFCCMUJpt1Hai4ySeEa
 jYkBqqbWXROmmvtE/sMSK04XUK74iVpJujn0jbbTEE2VNsMcQW0RmmSqS+7/Na7c
 LJdi7nTj/VKY55pxX/EjkMzXgE4GRbRxnQi9gETM0nSrklvRIAh7m1ePI0oh9K7Y
 2gHT0Zk0B9oKHFXOFPMKSjwwhf/WFW3Y/epcbnIqBfQWWd1+afc=
 =QSFw
 -----END PGP SIGNATURE-----

Merge tag 'clk-meson-fixes-v5.4-1' of https://github.com/BayLibre/clk-meson into clk-fixes

Pull first round of amlogic clock fixes from Jerome Brunet:

 - This fixes the clock rate propagation for the g12a cpu and gxbb adc clocks.

* tag 'clk-meson-fixes-v5.4-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
  clk: meson: g12a: fix cpu clock rate setting
  clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate

drivers/clk/meson/g12a.c

@@ -343,6 +343,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = {
 		.offset = HHI_SYS_CPU_CLK_CNTL0,
 		.mask = 0x3,
 		.shift = 0,
+		.flags = CLK_MUX_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk_dyn0_sel",
@@ -353,8 +354,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = {
 			{ .hw = &g12a_fclk_div3.hw },
 		},
 		.num_parents = 3,
-		/* This sub-tree is used a parking clock */
-		.flags = CLK_SET_RATE_NO_REPARENT,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -410,6 +410,7 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = {
 		.offset = HHI_SYS_CPU_CLK_CNTL0,
 		.mask = 0x1,
 		.shift = 2,
+		.flags = CLK_MUX_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk_dyn0",
@@ -466,6 +467,7 @@ static struct clk_regmap g12a_cpu_clk_dyn = {
 		.offset = HHI_SYS_CPU_CLK_CNTL0,
 		.mask = 0x1,
 		.shift = 10,
+		.flags = CLK_MUX_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk_dyn",
@@ -485,6 +487,7 @@ static struct clk_regmap g12a_cpu_clk = {
 		.offset = HHI_SYS_CPU_CLK_CNTL0,
 		.mask = 0x1,
 		.shift = 11,
+		.flags = CLK_MUX_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk",
@@ -504,6 +507,7 @@ static struct clk_regmap g12b_cpu_clk = {
 		.offset = HHI_SYS_CPU_CLK_CNTL0,
 		.mask = 0x1,
 		.shift = 11,
+		.flags = CLK_MUX_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk",
@@ -523,6 +527,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = {
 		.offset = HHI_SYS_CPUB_CLK_CNTL,
 		.mask = 0x3,
 		.shift = 0,
+		.flags = CLK_MUX_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpub_clk_dyn0_sel",
@@ -533,6 +538,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = {
 			{ .hw = &g12a_fclk_div3.hw },
 		},
 		.num_parents = 3,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -567,6 +573,7 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = {
 		.offset = HHI_SYS_CPUB_CLK_CNTL,
 		.mask = 0x1,
 		.shift = 2,
+		.flags = CLK_MUX_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpub_clk_dyn0",
@@ -644,6 +651,7 @@ static struct clk_regmap g12b_cpub_clk_dyn = {
 		.offset = HHI_SYS_CPUB_CLK_CNTL,
 		.mask = 0x1,
 		.shift = 10,
+		.flags = CLK_MUX_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpub_clk_dyn",
@@ -663,6 +671,7 @@ static struct clk_regmap g12b_cpub_clk = {
 		.offset = HHI_SYS_CPUB_CLK_CNTL,
 		.mask = 0x1,
 		.shift = 11,
+		.flags = CLK_MUX_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpub_clk",

drivers/clk/meson/gxbb.c

@@ -935,6 +935,7 @@ static struct clk_regmap gxbb_sar_adc_clk_div = {
 			&gxbb_sar_adc_clk_sel.hw
 		},
 		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };