mirror of https://gitee.com/openkylin/linux.git
Blackfin: clean up style in irq defines
These files had a lot of whitespace damage, mostly due to copying and pasting original files that had damage. The BF561 header also had a lot of unused CONFIG_DEF_xxx defines, so punt them all. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
6adc521e71
commit
3dd666067d
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
#include <mach-common/irq.h>
|
||||
|
||||
#define NR_PERI_INTS (2 * 32)
|
||||
#define NR_PERI_INTS (2 * 32)
|
||||
|
||||
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
|
||||
|
|
@ -25,23 +25,23 @@
|
|||
#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
|
||||
#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
|
||||
#define IRQ_RTC BFIN_IRQ(14) /* RTC */
|
||||
#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
|
||||
#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
|
||||
#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
|
||||
#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
|
||||
#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
|
||||
#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
|
||||
#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
|
||||
#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
|
||||
#define IRQ_TWI BFIN_IRQ(20) /* TWI */
|
||||
#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
|
||||
#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
|
||||
#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
|
||||
#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
|
||||
#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
|
||||
#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
|
||||
#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
|
||||
#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
|
||||
#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
|
||||
#define IRQ_TWI BFIN_IRQ(20) /* TWI */
|
||||
#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
|
||||
#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
|
||||
#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
|
||||
#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
|
||||
#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
|
||||
#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
|
||||
#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
|
||||
#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
|
||||
#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
|
||||
#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
|
||||
#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
|
||||
#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
|
||||
|
|
@ -67,90 +67,90 @@
|
|||
#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
|
||||
#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
|
||||
|
||||
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
|
||||
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
|
||||
|
||||
#define IRQ_PF0 71
|
||||
#define IRQ_PF1 72
|
||||
#define IRQ_PF2 73
|
||||
#define IRQ_PF3 74
|
||||
#define IRQ_PF4 75
|
||||
#define IRQ_PF5 76
|
||||
#define IRQ_PF6 77
|
||||
#define IRQ_PF7 78
|
||||
#define IRQ_PF8 79
|
||||
#define IRQ_PF9 80
|
||||
#define IRQ_PF10 81
|
||||
#define IRQ_PF11 82
|
||||
#define IRQ_PF12 83
|
||||
#define IRQ_PF13 84
|
||||
#define IRQ_PF14 85
|
||||
#define IRQ_PF15 86
|
||||
#define IRQ_PF0 71
|
||||
#define IRQ_PF1 72
|
||||
#define IRQ_PF2 73
|
||||
#define IRQ_PF3 74
|
||||
#define IRQ_PF4 75
|
||||
#define IRQ_PF5 76
|
||||
#define IRQ_PF6 77
|
||||
#define IRQ_PF7 78
|
||||
#define IRQ_PF8 79
|
||||
#define IRQ_PF9 80
|
||||
#define IRQ_PF10 81
|
||||
#define IRQ_PF11 82
|
||||
#define IRQ_PF12 83
|
||||
#define IRQ_PF13 84
|
||||
#define IRQ_PF14 85
|
||||
#define IRQ_PF15 86
|
||||
|
||||
#define IRQ_PG0 87
|
||||
#define IRQ_PG1 88
|
||||
#define IRQ_PG2 89
|
||||
#define IRQ_PG3 90
|
||||
#define IRQ_PG4 91
|
||||
#define IRQ_PG5 92
|
||||
#define IRQ_PG6 93
|
||||
#define IRQ_PG7 94
|
||||
#define IRQ_PG8 95
|
||||
#define IRQ_PG9 96
|
||||
#define IRQ_PG10 97
|
||||
#define IRQ_PG11 98
|
||||
#define IRQ_PG12 99
|
||||
#define IRQ_PG13 100
|
||||
#define IRQ_PG14 101
|
||||
#define IRQ_PG15 102
|
||||
#define IRQ_PG0 87
|
||||
#define IRQ_PG1 88
|
||||
#define IRQ_PG2 89
|
||||
#define IRQ_PG3 90
|
||||
#define IRQ_PG4 91
|
||||
#define IRQ_PG5 92
|
||||
#define IRQ_PG6 93
|
||||
#define IRQ_PG7 94
|
||||
#define IRQ_PG8 95
|
||||
#define IRQ_PG9 96
|
||||
#define IRQ_PG10 97
|
||||
#define IRQ_PG11 98
|
||||
#define IRQ_PG12 99
|
||||
#define IRQ_PG13 100
|
||||
#define IRQ_PG14 101
|
||||
#define IRQ_PG15 102
|
||||
|
||||
#define IRQ_PH0 103
|
||||
#define IRQ_PH1 104
|
||||
#define IRQ_PH2 105
|
||||
#define IRQ_PH3 106
|
||||
#define IRQ_PH4 107
|
||||
#define IRQ_PH5 108
|
||||
#define IRQ_PH6 109
|
||||
#define IRQ_PH7 110
|
||||
#define IRQ_PH8 111
|
||||
#define IRQ_PH9 112
|
||||
#define IRQ_PH10 113
|
||||
#define IRQ_PH11 114
|
||||
#define IRQ_PH12 115
|
||||
#define IRQ_PH13 116
|
||||
#define IRQ_PH14 117
|
||||
#define IRQ_PH15 118
|
||||
#define IRQ_PH0 103
|
||||
#define IRQ_PH1 104
|
||||
#define IRQ_PH2 105
|
||||
#define IRQ_PH3 106
|
||||
#define IRQ_PH4 107
|
||||
#define IRQ_PH5 108
|
||||
#define IRQ_PH6 109
|
||||
#define IRQ_PH7 110
|
||||
#define IRQ_PH8 111
|
||||
#define IRQ_PH9 112
|
||||
#define IRQ_PH10 113
|
||||
#define IRQ_PH11 114
|
||||
#define IRQ_PH12 115
|
||||
#define IRQ_PH13 116
|
||||
#define IRQ_PH14 117
|
||||
#define IRQ_PH15 118
|
||||
|
||||
#define GPIO_IRQ_BASE IRQ_PF0
|
||||
#define GPIO_IRQ_BASE IRQ_PF0
|
||||
|
||||
#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
|
||||
#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
|
||||
#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
|
||||
#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
|
||||
#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
|
||||
#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
|
||||
#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
|
||||
#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
|
||||
|
||||
#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
|
||||
#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
|
||||
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
#define IRQ_DMA0_ERROR_POS 4
|
||||
#define IRQ_DMAR0_BLK_POS 8
|
||||
#define IRQ_DMAR1_BLK_POS 12
|
||||
#define IRQ_DMAR0_OVR_POS 16
|
||||
#define IRQ_DMAR1_OVR_POS 20
|
||||
#define IRQ_PPI_ERROR_POS 24
|
||||
#define IRQ_MAC_ERROR_POS 28
|
||||
#define IRQ_DMAR0_BLK_POS 8
|
||||
#define IRQ_DMAR1_BLK_POS 12
|
||||
#define IRQ_DMAR0_OVR_POS 16
|
||||
#define IRQ_DMAR1_OVR_POS 20
|
||||
#define IRQ_PPI_ERROR_POS 24
|
||||
#define IRQ_MAC_ERROR_POS 28
|
||||
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define IRQ_SPORT0_ERROR_POS 0
|
||||
#define IRQ_SPORT1_ERROR_POS 4
|
||||
#define IRQ_PTP_ERROR_POS 8
|
||||
#define IRQ_UART0_ERROR_POS 16
|
||||
#define IRQ_UART1_ERROR_POS 20
|
||||
#define IRQ_RTC_POS 24
|
||||
#define IRQ_PPI_POS 28
|
||||
#define IRQ_UART0_ERROR_POS 16
|
||||
#define IRQ_UART1_ERROR_POS 20
|
||||
#define IRQ_RTC_POS 24
|
||||
#define IRQ_PPI_POS 28
|
||||
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define IRQ_SPORT0_RX_POS 0
|
||||
|
|
@ -159,19 +159,19 @@
|
|||
#define IRQ_SPORT1_RX_POS 8
|
||||
#define IRQ_SPI1_POS 8
|
||||
#define IRQ_SPORT1_TX_POS 12
|
||||
#define IRQ_TWI_POS 16
|
||||
#define IRQ_SPI0_POS 20
|
||||
#define IRQ_UART0_RX_POS 24
|
||||
#define IRQ_UART0_TX_POS 28
|
||||
#define IRQ_TWI_POS 16
|
||||
#define IRQ_SPI0_POS 20
|
||||
#define IRQ_UART0_RX_POS 24
|
||||
#define IRQ_UART0_TX_POS 28
|
||||
|
||||
/* IAR3 BIT FIELDS */
|
||||
#define IRQ_UART1_RX_POS 0
|
||||
#define IRQ_UART1_TX_POS 4
|
||||
#define IRQ_OPTSEC_POS 8
|
||||
#define IRQ_CNT_POS 12
|
||||
#define IRQ_MAC_RX_POS 16
|
||||
#define IRQ_UART1_RX_POS 0
|
||||
#define IRQ_UART1_TX_POS 4
|
||||
#define IRQ_OPTSEC_POS 8
|
||||
#define IRQ_CNT_POS 12
|
||||
#define IRQ_MAC_RX_POS 16
|
||||
#define IRQ_PORTH_INTA_POS 20
|
||||
#define IRQ_MAC_TX_POS 24
|
||||
#define IRQ_MAC_TX_POS 24
|
||||
#define IRQ_PORTH_INTB_POS 28
|
||||
|
||||
/* IAR4 BIT FIELDS */
|
||||
|
|
@ -187,19 +187,19 @@
|
|||
/* IAR5 BIT FIELDS */
|
||||
#define IRQ_PORTG_INTA_POS 0
|
||||
#define IRQ_PORTG_INTB_POS 4
|
||||
#define IRQ_MEM_DMA0_POS 8
|
||||
#define IRQ_MEM_DMA1_POS 12
|
||||
#define IRQ_WATCH_POS 16
|
||||
#define IRQ_MEM_DMA0_POS 8
|
||||
#define IRQ_MEM_DMA1_POS 12
|
||||
#define IRQ_WATCH_POS 16
|
||||
#define IRQ_PORTF_INTA_POS 20
|
||||
#define IRQ_PORTF_INTB_POS 24
|
||||
#define IRQ_SPI0_ERROR_POS 28
|
||||
#define IRQ_SPI0_ERROR_POS 28
|
||||
|
||||
/* IAR6 BIT FIELDS */
|
||||
#define IRQ_SPI1_ERROR_POS 0
|
||||
#define IRQ_RSI_INT0_POS 12
|
||||
#define IRQ_RSI_INT1_POS 16
|
||||
#define IRQ_PWM_TRIP_POS 20
|
||||
#define IRQ_PWM_SYNC_POS 24
|
||||
#define IRQ_PTP_STAT_POS 28
|
||||
#define IRQ_SPI1_ERROR_POS 0
|
||||
#define IRQ_RSI_INT0_POS 12
|
||||
#define IRQ_RSI_INT1_POS 16
|
||||
#define IRQ_PWM_TRIP_POS 20
|
||||
#define IRQ_PWM_SYNC_POS 24
|
||||
#define IRQ_PTP_STAT_POS 28
|
||||
|
||||
#endif /* _BF518_IRQ_H_ */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
#include <mach-common/irq.h>
|
||||
|
||||
#define NR_PERI_INTS (2 * 32)
|
||||
#define NR_PERI_INTS (2 * 32)
|
||||
|
||||
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
|
||||
|
|
@ -24,21 +24,21 @@
|
|||
#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
|
||||
#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
|
||||
#define IRQ_RTC BFIN_IRQ(14) /* RTC */
|
||||
#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
|
||||
#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
|
||||
#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
|
||||
#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
|
||||
#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
|
||||
#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
|
||||
#define IRQ_TWI BFIN_IRQ(20) /* TWI */
|
||||
#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
|
||||
#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
|
||||
#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
|
||||
#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
|
||||
#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
|
||||
#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
|
||||
#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
|
||||
#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
|
||||
#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
|
||||
#define IRQ_TWI BFIN_IRQ(20) /* TWI */
|
||||
#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
|
||||
#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
|
||||
#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
|
||||
#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
|
||||
#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
|
||||
#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
|
||||
#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
|
||||
#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
|
||||
#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
|
||||
#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
|
||||
#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
|
||||
#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
|
||||
|
|
@ -67,108 +67,108 @@
|
|||
#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
|
||||
#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
|
||||
|
||||
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
|
||||
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
|
||||
|
||||
#define IRQ_PF0 71
|
||||
#define IRQ_PF1 72
|
||||
#define IRQ_PF2 73
|
||||
#define IRQ_PF3 74
|
||||
#define IRQ_PF4 75
|
||||
#define IRQ_PF5 76
|
||||
#define IRQ_PF6 77
|
||||
#define IRQ_PF7 78
|
||||
#define IRQ_PF8 79
|
||||
#define IRQ_PF9 80
|
||||
#define IRQ_PF10 81
|
||||
#define IRQ_PF11 82
|
||||
#define IRQ_PF12 83
|
||||
#define IRQ_PF13 84
|
||||
#define IRQ_PF14 85
|
||||
#define IRQ_PF15 86
|
||||
#define IRQ_PF0 71
|
||||
#define IRQ_PF1 72
|
||||
#define IRQ_PF2 73
|
||||
#define IRQ_PF3 74
|
||||
#define IRQ_PF4 75
|
||||
#define IRQ_PF5 76
|
||||
#define IRQ_PF6 77
|
||||
#define IRQ_PF7 78
|
||||
#define IRQ_PF8 79
|
||||
#define IRQ_PF9 80
|
||||
#define IRQ_PF10 81
|
||||
#define IRQ_PF11 82
|
||||
#define IRQ_PF12 83
|
||||
#define IRQ_PF13 84
|
||||
#define IRQ_PF14 85
|
||||
#define IRQ_PF15 86
|
||||
|
||||
#define IRQ_PG0 87
|
||||
#define IRQ_PG1 88
|
||||
#define IRQ_PG2 89
|
||||
#define IRQ_PG3 90
|
||||
#define IRQ_PG4 91
|
||||
#define IRQ_PG5 92
|
||||
#define IRQ_PG6 93
|
||||
#define IRQ_PG7 94
|
||||
#define IRQ_PG8 95
|
||||
#define IRQ_PG9 96
|
||||
#define IRQ_PG10 97
|
||||
#define IRQ_PG11 98
|
||||
#define IRQ_PG12 99
|
||||
#define IRQ_PG13 100
|
||||
#define IRQ_PG14 101
|
||||
#define IRQ_PG15 102
|
||||
#define IRQ_PG0 87
|
||||
#define IRQ_PG1 88
|
||||
#define IRQ_PG2 89
|
||||
#define IRQ_PG3 90
|
||||
#define IRQ_PG4 91
|
||||
#define IRQ_PG5 92
|
||||
#define IRQ_PG6 93
|
||||
#define IRQ_PG7 94
|
||||
#define IRQ_PG8 95
|
||||
#define IRQ_PG9 96
|
||||
#define IRQ_PG10 97
|
||||
#define IRQ_PG11 98
|
||||
#define IRQ_PG12 99
|
||||
#define IRQ_PG13 100
|
||||
#define IRQ_PG14 101
|
||||
#define IRQ_PG15 102
|
||||
|
||||
#define IRQ_PH0 103
|
||||
#define IRQ_PH1 104
|
||||
#define IRQ_PH2 105
|
||||
#define IRQ_PH3 106
|
||||
#define IRQ_PH4 107
|
||||
#define IRQ_PH5 108
|
||||
#define IRQ_PH6 109
|
||||
#define IRQ_PH7 110
|
||||
#define IRQ_PH8 111
|
||||
#define IRQ_PH9 112
|
||||
#define IRQ_PH10 113
|
||||
#define IRQ_PH11 114
|
||||
#define IRQ_PH12 115
|
||||
#define IRQ_PH13 116
|
||||
#define IRQ_PH14 117
|
||||
#define IRQ_PH15 118
|
||||
#define IRQ_PH0 103
|
||||
#define IRQ_PH1 104
|
||||
#define IRQ_PH2 105
|
||||
#define IRQ_PH3 106
|
||||
#define IRQ_PH4 107
|
||||
#define IRQ_PH5 108
|
||||
#define IRQ_PH6 109
|
||||
#define IRQ_PH7 110
|
||||
#define IRQ_PH8 111
|
||||
#define IRQ_PH9 112
|
||||
#define IRQ_PH10 113
|
||||
#define IRQ_PH11 114
|
||||
#define IRQ_PH12 115
|
||||
#define IRQ_PH13 116
|
||||
#define IRQ_PH14 117
|
||||
#define IRQ_PH15 118
|
||||
|
||||
#define GPIO_IRQ_BASE IRQ_PF0
|
||||
#define GPIO_IRQ_BASE IRQ_PF0
|
||||
|
||||
#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
|
||||
#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
|
||||
#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
|
||||
#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
|
||||
#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
|
||||
#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
|
||||
#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
|
||||
#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
|
||||
|
||||
#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
|
||||
#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
|
||||
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
#define IRQ_DMA0_ERROR_POS 4
|
||||
#define IRQ_DMAR0_BLK_POS 8
|
||||
#define IRQ_DMAR1_BLK_POS 12
|
||||
#define IRQ_DMAR0_OVR_POS 16
|
||||
#define IRQ_DMAR1_OVR_POS 20
|
||||
#define IRQ_PPI_ERROR_POS 24
|
||||
#define IRQ_MAC_ERROR_POS 28
|
||||
#define IRQ_DMAR0_BLK_POS 8
|
||||
#define IRQ_DMAR1_BLK_POS 12
|
||||
#define IRQ_DMAR0_OVR_POS 16
|
||||
#define IRQ_DMAR1_OVR_POS 20
|
||||
#define IRQ_PPI_ERROR_POS 24
|
||||
#define IRQ_MAC_ERROR_POS 28
|
||||
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define IRQ_SPORT0_ERROR_POS 0
|
||||
#define IRQ_SPORT1_ERROR_POS 4
|
||||
#define IRQ_UART0_ERROR_POS 16
|
||||
#define IRQ_UART1_ERROR_POS 20
|
||||
#define IRQ_RTC_POS 24
|
||||
#define IRQ_PPI_POS 28
|
||||
#define IRQ_UART0_ERROR_POS 16
|
||||
#define IRQ_UART1_ERROR_POS 20
|
||||
#define IRQ_RTC_POS 24
|
||||
#define IRQ_PPI_POS 28
|
||||
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define IRQ_SPORT0_RX_POS 0
|
||||
#define IRQ_SPORT0_TX_POS 4
|
||||
#define IRQ_SPORT1_RX_POS 8
|
||||
#define IRQ_SPORT1_TX_POS 12
|
||||
#define IRQ_TWI_POS 16
|
||||
#define IRQ_SPI_POS 20
|
||||
#define IRQ_UART0_RX_POS 24
|
||||
#define IRQ_UART0_TX_POS 28
|
||||
#define IRQ_TWI_POS 16
|
||||
#define IRQ_SPI_POS 20
|
||||
#define IRQ_UART0_RX_POS 24
|
||||
#define IRQ_UART0_TX_POS 28
|
||||
|
||||
/* IAR3 BIT FIELDS */
|
||||
#define IRQ_UART1_RX_POS 0
|
||||
#define IRQ_UART1_TX_POS 4
|
||||
#define IRQ_OPTSEC_POS 8
|
||||
#define IRQ_CNT_POS 12
|
||||
#define IRQ_MAC_RX_POS 16
|
||||
#define IRQ_UART1_RX_POS 0
|
||||
#define IRQ_UART1_TX_POS 4
|
||||
#define IRQ_OPTSEC_POS 8
|
||||
#define IRQ_CNT_POS 12
|
||||
#define IRQ_MAC_RX_POS 16
|
||||
#define IRQ_PORTH_INTA_POS 20
|
||||
#define IRQ_MAC_TX_POS 24
|
||||
#define IRQ_MAC_TX_POS 24
|
||||
#define IRQ_PORTH_INTB_POS 28
|
||||
|
||||
/* IAR4 BIT FIELDS */
|
||||
|
|
@ -184,21 +184,21 @@
|
|||
/* IAR5 BIT FIELDS */
|
||||
#define IRQ_PORTG_INTA_POS 0
|
||||
#define IRQ_PORTG_INTB_POS 4
|
||||
#define IRQ_MEM_DMA0_POS 8
|
||||
#define IRQ_MEM_DMA1_POS 12
|
||||
#define IRQ_WATCH_POS 16
|
||||
#define IRQ_MEM_DMA0_POS 8
|
||||
#define IRQ_MEM_DMA1_POS 12
|
||||
#define IRQ_WATCH_POS 16
|
||||
#define IRQ_PORTF_INTA_POS 20
|
||||
#define IRQ_PORTF_INTB_POS 24
|
||||
#define IRQ_SPI_ERROR_POS 28
|
||||
#define IRQ_SPI_ERROR_POS 28
|
||||
|
||||
/* IAR6 BIT FIELDS */
|
||||
#define IRQ_NFC_ERROR_POS 0
|
||||
#define IRQ_HDMA_ERROR_POS 4
|
||||
#define IRQ_HDMA_POS 8
|
||||
#define IRQ_USB_EINT_POS 12
|
||||
#define IRQ_USB_INT0_POS 16
|
||||
#define IRQ_USB_INT1_POS 20
|
||||
#define IRQ_USB_INT2_POS 24
|
||||
#define IRQ_USB_DMA_POS 28
|
||||
#define IRQ_NFC_ERROR_POS 0
|
||||
#define IRQ_HDMA_ERROR_POS 4
|
||||
#define IRQ_HDMA_POS 8
|
||||
#define IRQ_USB_EINT_POS 12
|
||||
#define IRQ_USB_INT0_POS 16
|
||||
#define IRQ_USB_INT1_POS 20
|
||||
#define IRQ_USB_INT2_POS 24
|
||||
#define IRQ_USB_DMA_POS 28
|
||||
|
||||
#endif /* _BF527_IRQ_H_ */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,33 +9,34 @@
|
|||
|
||||
#include <mach-common/irq.h>
|
||||
|
||||
#define SYS_IRQS 31
|
||||
#define NR_PERI_INTS 24
|
||||
#define NR_PERI_INTS 24
|
||||
|
||||
#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
|
||||
#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
|
||||
#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
|
||||
#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
|
||||
#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
|
||||
#define IRQ_UART0_ERROR 13 /*UART Error Interrupt */
|
||||
#define IRQ_RTC 14 /*RTC Interrupt */
|
||||
#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
|
||||
#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
|
||||
#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
|
||||
#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
|
||||
#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
|
||||
#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
|
||||
#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */
|
||||
#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */
|
||||
#define IRQ_TIMER0 23 /*Timer 0 */
|
||||
#define IRQ_TIMER1 24 /*Timer 1 */
|
||||
#define IRQ_TIMER2 25 /*Timer 2 */
|
||||
#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
|
||||
#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
|
||||
#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
|
||||
#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
|
||||
#define IRQ_WATCH 30 /*Watch Dog Timer */
|
||||
#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA_ERROR 8 /* DMA Error (general) */
|
||||
#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */
|
||||
#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */
|
||||
#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */
|
||||
#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */
|
||||
#define IRQ_UART0_ERROR 13 /* UART Error Interrupt */
|
||||
#define IRQ_RTC 14 /* RTC Interrupt */
|
||||
#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */
|
||||
#define IRQ_SPORT0_RX 16 /* DMA1 Interrupt (SPORT0 RX) */
|
||||
#define IRQ_SPORT0_TX 17 /* DMA2 Interrupt (SPORT0 TX) */
|
||||
#define IRQ_SPORT1_RX 18 /* DMA3 Interrupt (SPORT1 RX) */
|
||||
#define IRQ_SPORT1_TX 19 /* DMA4 Interrupt (SPORT1 TX) */
|
||||
#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */
|
||||
#define IRQ_UART0_RX 21 /* DMA6 Interrupt (UART RX) */
|
||||
#define IRQ_UART0_TX 22 /* DMA7 Interrupt (UART TX) */
|
||||
#define IRQ_TIMER0 23 /* Timer 0 */
|
||||
#define IRQ_TIMER1 24 /* Timer 1 */
|
||||
#define IRQ_TIMER2 25 /* Timer 2 */
|
||||
#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */
|
||||
#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */
|
||||
#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */
|
||||
#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */
|
||||
#define IRQ_WATCH 30 /* Watch Dog Timer */
|
||||
|
||||
#define SYS_IRQS 31
|
||||
|
||||
#define IRQ_PF0 33
|
||||
#define IRQ_PF1 34
|
||||
|
|
@ -58,34 +59,34 @@
|
|||
|
||||
#define NR_MACH_IRQS (IRQ_PF15 + 1)
|
||||
|
||||
/* IAR0 BIT FIELDS*/
|
||||
#define RTC_ERROR_POS 28
|
||||
#define UART_ERROR_POS 24
|
||||
#define SPORT1_ERROR_POS 20
|
||||
#define SPI_ERROR_POS 16
|
||||
#define SPORT0_ERROR_POS 12
|
||||
#define PPI_ERROR_POS 8
|
||||
#define DMA_ERROR_POS 4
|
||||
#define PLLWAKE_ERROR_POS 0
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define RTC_ERROR_POS 28
|
||||
#define UART_ERROR_POS 24
|
||||
#define SPORT1_ERROR_POS 20
|
||||
#define SPI_ERROR_POS 16
|
||||
#define SPORT0_ERROR_POS 12
|
||||
#define PPI_ERROR_POS 8
|
||||
#define DMA_ERROR_POS 4
|
||||
#define PLLWAKE_ERROR_POS 0
|
||||
|
||||
/* IAR1 BIT FIELDS*/
|
||||
#define DMA7_UARTTX_POS 28
|
||||
#define DMA6_UARTRX_POS 24
|
||||
#define DMA5_SPI_POS 20
|
||||
#define DMA4_SPORT1TX_POS 16
|
||||
#define DMA3_SPORT1RX_POS 12
|
||||
#define DMA2_SPORT0TX_POS 8
|
||||
#define DMA1_SPORT0RX_POS 4
|
||||
#define DMA0_PPI_POS 0
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define DMA7_UARTTX_POS 28
|
||||
#define DMA6_UARTRX_POS 24
|
||||
#define DMA5_SPI_POS 20
|
||||
#define DMA4_SPORT1TX_POS 16
|
||||
#define DMA3_SPORT1RX_POS 12
|
||||
#define DMA2_SPORT0TX_POS 8
|
||||
#define DMA1_SPORT0RX_POS 4
|
||||
#define DMA0_PPI_POS 0
|
||||
|
||||
/* IAR2 BIT FIELDS*/
|
||||
#define WDTIMER_POS 28
|
||||
#define MEMDMA1_POS 24
|
||||
#define MEMDMA0_POS 20
|
||||
#define PFB_POS 16
|
||||
#define PFA_POS 12
|
||||
#define TIMER2_POS 8
|
||||
#define TIMER1_POS 4
|
||||
#define TIMER0_POS 0
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define WDTIMER_POS 28
|
||||
#define MEMDMA1_POS 24
|
||||
#define MEMDMA0_POS 20
|
||||
#define PFB_POS 16
|
||||
#define PFA_POS 12
|
||||
#define TIMER2_POS 8
|
||||
#define TIMER1_POS 4
|
||||
#define TIMER0_POS 0
|
||||
|
||||
#endif /* _BF533_IRQ_H_ */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,154 +9,155 @@
|
|||
|
||||
#include <mach-common/irq.h>
|
||||
|
||||
#define SYS_IRQS 39
|
||||
#define NR_PERI_INTS 32
|
||||
#define NR_PERI_INTS 32
|
||||
|
||||
#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
|
||||
#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
|
||||
#define IRQ_RTC 10 /*RTC Interrupt */
|
||||
#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */
|
||||
#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */
|
||||
#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */
|
||||
#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */
|
||||
#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */
|
||||
#define IRQ_TWI 16 /*TWI Interrupt */
|
||||
#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */
|
||||
#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */
|
||||
#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */
|
||||
#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */
|
||||
#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */
|
||||
#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */
|
||||
#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
|
||||
#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
|
||||
#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
|
||||
#define IRQ_TIMER0 26 /*Timer 0 */
|
||||
#define IRQ_TIMER1 27 /*Timer 1 */
|
||||
#define IRQ_TIMER2 28 /*Timer 2 */
|
||||
#define IRQ_TIMER3 29 /*Timer 3 */
|
||||
#define IRQ_TIMER4 30 /*Timer 4 */
|
||||
#define IRQ_TIMER5 31 /*Timer 5 */
|
||||
#define IRQ_TIMER6 32 /*Timer 6 */
|
||||
#define IRQ_TIMER7 33 /*Timer 7 */
|
||||
#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
|
||||
#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
|
||||
#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
|
||||
#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
|
||||
#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
|
||||
#define IRQ_WATCH 38 /*Watch Dog Timer */
|
||||
#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA_ERROR 8 /* DMA Error (general) */
|
||||
#define IRQ_GENERIC_ERROR 9 /* GENERIC Error Interrupt */
|
||||
#define IRQ_RTC 10 /* RTC Interrupt */
|
||||
#define IRQ_PPI 11 /* DMA0 Interrupt (PPI) */
|
||||
#define IRQ_SPORT0_RX 12 /* DMA3 Interrupt (SPORT0 RX) */
|
||||
#define IRQ_SPORT0_TX 13 /* DMA4 Interrupt (SPORT0 TX) */
|
||||
#define IRQ_SPORT1_RX 14 /* DMA5 Interrupt (SPORT1 RX) */
|
||||
#define IRQ_SPORT1_TX 15 /* DMA6 Interrupt (SPORT1 TX) */
|
||||
#define IRQ_TWI 16 /* TWI Interrupt */
|
||||
#define IRQ_SPI 17 /* DMA7 Interrupt (SPI) */
|
||||
#define IRQ_UART0_RX 18 /* DMA8 Interrupt (UART0 RX) */
|
||||
#define IRQ_UART0_TX 19 /* DMA9 Interrupt (UART0 TX) */
|
||||
#define IRQ_UART1_RX 20 /* DMA10 Interrupt (UART1 RX) */
|
||||
#define IRQ_UART1_TX 21 /* DMA11 Interrupt (UART1 TX) */
|
||||
#define IRQ_CAN_RX 22 /* CAN Receive Interrupt */
|
||||
#define IRQ_CAN_TX 23 /* CAN Transmit Interrupt */
|
||||
#define IRQ_MAC_RX 24 /* DMA1 (Ethernet RX) Interrupt */
|
||||
#define IRQ_MAC_TX 25 /* DMA2 (Ethernet TX) Interrupt */
|
||||
#define IRQ_TIMER0 26 /* Timer 0 */
|
||||
#define IRQ_TIMER1 27 /* Timer 1 */
|
||||
#define IRQ_TIMER2 28 /* Timer 2 */
|
||||
#define IRQ_TIMER3 29 /* Timer 3 */
|
||||
#define IRQ_TIMER4 30 /* Timer 4 */
|
||||
#define IRQ_TIMER5 31 /* Timer 5 */
|
||||
#define IRQ_TIMER6 32 /* Timer 6 */
|
||||
#define IRQ_TIMER7 33 /* Timer 7 */
|
||||
#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
|
||||
#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
|
||||
#define IRQ_MEM_DMA0 36 /* (Memory DMA Stream 0) */
|
||||
#define IRQ_MEM_DMA1 37 /* (Memory DMA Stream 1) */
|
||||
#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
|
||||
#define IRQ_WATCH 38 /* Watch Dog Timer */
|
||||
|
||||
#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
|
||||
#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
|
||||
#define IRQ_MAC_ERROR 44 /*MAC Status/Error Interrupt */
|
||||
#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
|
||||
#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
|
||||
#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
|
||||
#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */
|
||||
#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */
|
||||
#define SYS_IRQS 39
|
||||
|
||||
#define IRQ_PF0 50
|
||||
#define IRQ_PF1 51
|
||||
#define IRQ_PF2 52
|
||||
#define IRQ_PF3 53
|
||||
#define IRQ_PF4 54
|
||||
#define IRQ_PF5 55
|
||||
#define IRQ_PF6 56
|
||||
#define IRQ_PF7 57
|
||||
#define IRQ_PF8 58
|
||||
#define IRQ_PF9 59
|
||||
#define IRQ_PF10 60
|
||||
#define IRQ_PF11 61
|
||||
#define IRQ_PF12 62
|
||||
#define IRQ_PF13 63
|
||||
#define IRQ_PF14 64
|
||||
#define IRQ_PF15 65
|
||||
#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
|
||||
#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
|
||||
#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
|
||||
#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
|
||||
#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
|
||||
#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
|
||||
#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
|
||||
#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
|
||||
|
||||
#define IRQ_PG0 66
|
||||
#define IRQ_PG1 67
|
||||
#define IRQ_PG2 68
|
||||
#define IRQ_PG3 69
|
||||
#define IRQ_PG4 70
|
||||
#define IRQ_PG5 71
|
||||
#define IRQ_PG6 72
|
||||
#define IRQ_PG7 73
|
||||
#define IRQ_PG8 74
|
||||
#define IRQ_PG9 75
|
||||
#define IRQ_PG10 76
|
||||
#define IRQ_PG11 77
|
||||
#define IRQ_PG12 78
|
||||
#define IRQ_PG13 79
|
||||
#define IRQ_PG14 80
|
||||
#define IRQ_PG15 81
|
||||
#define IRQ_PF0 50
|
||||
#define IRQ_PF1 51
|
||||
#define IRQ_PF2 52
|
||||
#define IRQ_PF3 53
|
||||
#define IRQ_PF4 54
|
||||
#define IRQ_PF5 55
|
||||
#define IRQ_PF6 56
|
||||
#define IRQ_PF7 57
|
||||
#define IRQ_PF8 58
|
||||
#define IRQ_PF9 59
|
||||
#define IRQ_PF10 60
|
||||
#define IRQ_PF11 61
|
||||
#define IRQ_PF12 62
|
||||
#define IRQ_PF13 63
|
||||
#define IRQ_PF14 64
|
||||
#define IRQ_PF15 65
|
||||
|
||||
#define IRQ_PH0 82
|
||||
#define IRQ_PH1 83
|
||||
#define IRQ_PH2 84
|
||||
#define IRQ_PH3 85
|
||||
#define IRQ_PH4 86
|
||||
#define IRQ_PH5 87
|
||||
#define IRQ_PH6 88
|
||||
#define IRQ_PH7 89
|
||||
#define IRQ_PH8 90
|
||||
#define IRQ_PH9 91
|
||||
#define IRQ_PH10 92
|
||||
#define IRQ_PH11 93
|
||||
#define IRQ_PH12 94
|
||||
#define IRQ_PH13 95
|
||||
#define IRQ_PH14 96
|
||||
#define IRQ_PH15 97
|
||||
#define IRQ_PG0 66
|
||||
#define IRQ_PG1 67
|
||||
#define IRQ_PG2 68
|
||||
#define IRQ_PG3 69
|
||||
#define IRQ_PG4 70
|
||||
#define IRQ_PG5 71
|
||||
#define IRQ_PG6 72
|
||||
#define IRQ_PG7 73
|
||||
#define IRQ_PG8 74
|
||||
#define IRQ_PG9 75
|
||||
#define IRQ_PG10 76
|
||||
#define IRQ_PG11 77
|
||||
#define IRQ_PG12 78
|
||||
#define IRQ_PG13 79
|
||||
#define IRQ_PG14 80
|
||||
#define IRQ_PG15 81
|
||||
|
||||
#define GPIO_IRQ_BASE IRQ_PF0
|
||||
#define IRQ_PH0 82
|
||||
#define IRQ_PH1 83
|
||||
#define IRQ_PH2 84
|
||||
#define IRQ_PH3 85
|
||||
#define IRQ_PH4 86
|
||||
#define IRQ_PH5 87
|
||||
#define IRQ_PH6 88
|
||||
#define IRQ_PH7 89
|
||||
#define IRQ_PH8 90
|
||||
#define IRQ_PH9 91
|
||||
#define IRQ_PH10 92
|
||||
#define IRQ_PH11 93
|
||||
#define IRQ_PH12 94
|
||||
#define IRQ_PH13 95
|
||||
#define IRQ_PH14 96
|
||||
#define IRQ_PH15 97
|
||||
|
||||
#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
|
||||
#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
|
||||
#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
|
||||
#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
|
||||
#define GPIO_IRQ_BASE IRQ_PF0
|
||||
|
||||
#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
|
||||
#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
|
||||
#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
|
||||
#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
|
||||
#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
|
||||
#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
|
||||
#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
|
||||
|
||||
/* IAR0 BIT FIELDS*/
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
#define IRQ_DMA_ERROR_POS 4
|
||||
#define IRQ_ERROR_POS 8
|
||||
#define IRQ_RTC_POS 12
|
||||
#define IRQ_PPI_POS 16
|
||||
#define IRQ_SPORT0_RX_POS 20
|
||||
#define IRQ_SPORT0_TX_POS 24
|
||||
#define IRQ_SPORT1_RX_POS 28
|
||||
#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
|
||||
|
||||
/* IAR1 BIT FIELDS*/
|
||||
#define IRQ_SPORT1_TX_POS 0
|
||||
#define IRQ_TWI_POS 4
|
||||
#define IRQ_SPI_POS 8
|
||||
#define IRQ_UART0_RX_POS 12
|
||||
#define IRQ_UART0_TX_POS 16
|
||||
#define IRQ_UART1_RX_POS 20
|
||||
#define IRQ_UART1_TX_POS 24
|
||||
#define IRQ_CAN_RX_POS 28
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
#define IRQ_DMA_ERROR_POS 4
|
||||
#define IRQ_ERROR_POS 8
|
||||
#define IRQ_RTC_POS 12
|
||||
#define IRQ_PPI_POS 16
|
||||
#define IRQ_SPORT0_RX_POS 20
|
||||
#define IRQ_SPORT0_TX_POS 24
|
||||
#define IRQ_SPORT1_RX_POS 28
|
||||
|
||||
/* IAR2 BIT FIELDS*/
|
||||
#define IRQ_CAN_TX_POS 0
|
||||
#define IRQ_MAC_RX_POS 4
|
||||
#define IRQ_MAC_TX_POS 8
|
||||
#define IRQ_TIMER0_POS 12
|
||||
#define IRQ_TIMER1_POS 16
|
||||
#define IRQ_TIMER2_POS 20
|
||||
#define IRQ_TIMER3_POS 24
|
||||
#define IRQ_TIMER4_POS 28
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define IRQ_SPORT1_TX_POS 0
|
||||
#define IRQ_TWI_POS 4
|
||||
#define IRQ_SPI_POS 8
|
||||
#define IRQ_UART0_RX_POS 12
|
||||
#define IRQ_UART0_TX_POS 16
|
||||
#define IRQ_UART1_RX_POS 20
|
||||
#define IRQ_UART1_TX_POS 24
|
||||
#define IRQ_CAN_RX_POS 28
|
||||
|
||||
/* IAR3 BIT FIELDS*/
|
||||
#define IRQ_TIMER5_POS 0
|
||||
#define IRQ_TIMER6_POS 4
|
||||
#define IRQ_TIMER7_POS 8
|
||||
#define IRQ_PROG_INTA_POS 12
|
||||
#define IRQ_PORTG_INTB_POS 16
|
||||
#define IRQ_MEM_DMA0_POS 20
|
||||
#define IRQ_MEM_DMA1_POS 24
|
||||
#define IRQ_WATCH_POS 28
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define IRQ_CAN_TX_POS 0
|
||||
#define IRQ_MAC_RX_POS 4
|
||||
#define IRQ_MAC_TX_POS 8
|
||||
#define IRQ_TIMER0_POS 12
|
||||
#define IRQ_TIMER1_POS 16
|
||||
#define IRQ_TIMER2_POS 20
|
||||
#define IRQ_TIMER3_POS 24
|
||||
#define IRQ_TIMER4_POS 28
|
||||
|
||||
#endif /* _BF537_IRQ_H_ */
|
||||
/* IAR3 BIT FIELDS */
|
||||
#define IRQ_TIMER5_POS 0
|
||||
#define IRQ_TIMER6_POS 4
|
||||
#define IRQ_TIMER7_POS 8
|
||||
#define IRQ_PROG_INTA_POS 12
|
||||
#define IRQ_PORTG_INTB_POS 16
|
||||
#define IRQ_MEM_DMA0_POS 20
|
||||
#define IRQ_MEM_DMA1_POS 24
|
||||
#define IRQ_WATCH_POS 28
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
#include <mach-common/irq.h>
|
||||
|
||||
#define NR_PERI_INTS (2 * 32)
|
||||
#define NR_PERI_INTS (2 * 32)
|
||||
|
||||
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
|
||||
|
|
@ -62,26 +62,26 @@
|
|||
|
||||
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
|
||||
|
||||
#define IRQ_PF0 71
|
||||
#define IRQ_PF1 72
|
||||
#define IRQ_PF2 73
|
||||
#define IRQ_PF3 74
|
||||
#define IRQ_PF4 75
|
||||
#define IRQ_PF5 76
|
||||
#define IRQ_PF6 77
|
||||
#define IRQ_PF7 78
|
||||
#define IRQ_PF8 79
|
||||
#define IRQ_PF9 80
|
||||
#define IRQ_PF10 81
|
||||
#define IRQ_PF11 82
|
||||
#define IRQ_PF12 83
|
||||
#define IRQ_PF13 84
|
||||
#define IRQ_PF14 85
|
||||
#define IRQ_PF15 86
|
||||
#define IRQ_PF0 71
|
||||
#define IRQ_PF1 72
|
||||
#define IRQ_PF2 73
|
||||
#define IRQ_PF3 74
|
||||
#define IRQ_PF4 75
|
||||
#define IRQ_PF5 76
|
||||
#define IRQ_PF6 77
|
||||
#define IRQ_PF7 78
|
||||
#define IRQ_PF8 79
|
||||
#define IRQ_PF9 80
|
||||
#define IRQ_PF10 81
|
||||
#define IRQ_PF11 82
|
||||
#define IRQ_PF12 83
|
||||
#define IRQ_PF13 84
|
||||
#define IRQ_PF14 85
|
||||
#define IRQ_PF15 86
|
||||
|
||||
#define GPIO_IRQ_BASE IRQ_PF0
|
||||
#define GPIO_IRQ_BASE IRQ_PF0
|
||||
|
||||
#define NR_MACH_IRQS (IRQ_PF15 + 1)
|
||||
#define NR_MACH_IRQS (IRQ_PF15 + 1)
|
||||
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
|
|
@ -144,4 +144,5 @@
|
|||
#define IRQ_CAN_TX_POS 0
|
||||
#define IRQ_MEM1_DMA0_POS 4
|
||||
#define IRQ_MEM1_DMA1_POS 8
|
||||
#endif /* _BF538_IRQ_H_ */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
#include <mach-common/irq.h>
|
||||
|
||||
#define NR_PERI_INTS (32 * 3)
|
||||
#define NR_PERI_INTS (3 * 32)
|
||||
|
||||
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
|
||||
|
|
@ -282,35 +282,35 @@
|
|||
#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
|
||||
#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
|
||||
|
||||
#define GPIO_IRQ_BASE IRQ_PA0
|
||||
#define GPIO_IRQ_BASE IRQ_PA0
|
||||
|
||||
#define NR_MACH_IRQS (IRQ_PJ15 + 1)
|
||||
#define NR_MACH_IRQS (IRQ_PJ15 + 1)
|
||||
|
||||
/* For compatibility reasons with existing code */
|
||||
|
||||
#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
|
||||
#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
|
||||
#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
|
||||
#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
|
||||
#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
|
||||
#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
|
||||
#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
|
||||
#define IRQ_UART0_ERR IRQ_UART0_ERROR
|
||||
#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
|
||||
#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
|
||||
#define IRQ_UART0_ERR IRQ_UART0_ERROR
|
||||
#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
|
||||
#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
|
||||
#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
|
||||
#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
|
||||
#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
|
||||
#define IRQ_UART1_ERR IRQ_UART1_ERROR
|
||||
#define IRQ_UART2_ERR IRQ_UART2_ERROR
|
||||
#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
|
||||
#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
|
||||
#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
|
||||
#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
|
||||
#define IRQ_UART3_ERR IRQ_UART3_ERROR
|
||||
#define IRQ_HOST_ERR IRQ_HOST_ERROR
|
||||
#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
|
||||
#define IRQ_NFC_ERR IRQ_NFC_ERROR
|
||||
#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
|
||||
#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
|
||||
#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
|
||||
#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
|
||||
#define IRQ_UART1_ERR IRQ_UART1_ERROR
|
||||
#define IRQ_UART2_ERR IRQ_UART2_ERROR
|
||||
#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
|
||||
#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
|
||||
#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
|
||||
#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
|
||||
#define IRQ_UART3_ERR IRQ_UART3_ERROR
|
||||
#define IRQ_HOST_ERR IRQ_HOST_ERROR
|
||||
#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
|
||||
#define IRQ_NFC_ERR IRQ_NFC_ERROR
|
||||
#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
|
||||
#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
|
||||
#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
|
||||
|
||||
/* IAR0 BIT FIELDS */
|
||||
|
|
@ -451,4 +451,4 @@ struct bfin_pint_regs {
|
|||
|
||||
#endif
|
||||
|
||||
#endif /* _BF548_IRQ_H_ */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,106 +9,97 @@
|
|||
|
||||
#include <mach-common/irq.h>
|
||||
|
||||
#define SYS_IRQS 71
|
||||
#define NR_PERI_INTS 64
|
||||
#define NR_PERI_INTS (2 * 32)
|
||||
|
||||
#define IVG_BASE 7
|
||||
/* IVG 7 */
|
||||
#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
|
||||
#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
|
||||
#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */
|
||||
#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */
|
||||
#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */
|
||||
#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
|
||||
#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */
|
||||
#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */
|
||||
#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
|
||||
#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
|
||||
#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
|
||||
#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */
|
||||
/* IVG 8 */
|
||||
#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
|
||||
#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
|
||||
#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
|
||||
#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */
|
||||
#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
|
||||
#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */
|
||||
#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */
|
||||
#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */
|
||||
#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */
|
||||
#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */
|
||||
#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */
|
||||
#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */
|
||||
#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
|
||||
#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
|
||||
#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
|
||||
/* IVG 9 */
|
||||
#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
|
||||
#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
|
||||
#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
|
||||
#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
|
||||
#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */
|
||||
#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
|
||||
#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */
|
||||
#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
|
||||
#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */
|
||||
#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
|
||||
#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */
|
||||
#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
|
||||
#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */
|
||||
#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
|
||||
#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */
|
||||
#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */
|
||||
#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
|
||||
#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
|
||||
#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
|
||||
/* IVG 10 */
|
||||
#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
|
||||
#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
|
||||
#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
|
||||
#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */
|
||||
#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */
|
||||
#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */
|
||||
#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */
|
||||
#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */
|
||||
#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */
|
||||
#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
|
||||
#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
|
||||
#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
|
||||
/* IVG 11 */
|
||||
#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
|
||||
#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
|
||||
#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
|
||||
#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
|
||||
#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */
|
||||
#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
|
||||
#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
|
||||
#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
|
||||
/* IVG 8 */
|
||||
#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
|
||||
#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
|
||||
#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
|
||||
#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
|
||||
#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
|
||||
#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */
|
||||
#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */
|
||||
#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */
|
||||
#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
|
||||
#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */
|
||||
#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */
|
||||
#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
|
||||
#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
|
||||
#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
|
||||
#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed */
|
||||
#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
|
||||
#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
|
||||
#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
|
||||
#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */
|
||||
#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
|
||||
#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */
|
||||
#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */
|
||||
#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */
|
||||
#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */
|
||||
#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */
|
||||
#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */
|
||||
#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */
|
||||
#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
|
||||
#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
|
||||
#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
|
||||
#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
|
||||
#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
|
||||
#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
|
||||
#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
|
||||
#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */
|
||||
#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
|
||||
#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */
|
||||
#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
|
||||
#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */
|
||||
#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
|
||||
#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */
|
||||
#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
|
||||
#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */
|
||||
#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
|
||||
#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */
|
||||
#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */
|
||||
#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
|
||||
#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
|
||||
#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
|
||||
#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
|
||||
#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
|
||||
#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
|
||||
#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */
|
||||
#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */
|
||||
#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */
|
||||
#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */
|
||||
#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */
|
||||
#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */
|
||||
#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
|
||||
#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
|
||||
#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
|
||||
#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
|
||||
#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
|
||||
#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
|
||||
#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
|
||||
#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */
|
||||
#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
|
||||
#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
|
||||
#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
|
||||
#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
|
||||
#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
|
||||
#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
|
||||
#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */
|
||||
#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
|
||||
#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */
|
||||
#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
|
||||
#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
|
||||
/* IVG 9 */
|
||||
#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
|
||||
#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
|
||||
#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
|
||||
#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */
|
||||
#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */
|
||||
#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
|
||||
/* IVG 12 */
|
||||
#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
|
||||
#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
|
||||
#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
|
||||
#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */
|
||||
#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */
|
||||
#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
|
||||
/* IVG 13 */
|
||||
#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */
|
||||
/* IVG 7 */
|
||||
#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */
|
||||
#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
|
||||
#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */
|
||||
#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */
|
||||
#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
|
||||
#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
|
||||
#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */
|
||||
#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* Supplemental interrupt 1 */
|
||||
|
||||
#define SYS_IRQS 71
|
||||
|
||||
#define IRQ_PF0 73
|
||||
#define IRQ_PF1 74
|
||||
|
|
@ -163,146 +154,84 @@
|
|||
|
||||
#define NR_MACH_IRQS (IRQ_PF47 + 1)
|
||||
|
||||
/*
|
||||
* DEFAULT PRIORITIES:
|
||||
*/
|
||||
|
||||
#define CONFIG_DEF_PLL_WAKEUP 7
|
||||
#define CONFIG_DEF_DMA1_ERROR 7
|
||||
#define CONFIG_DEF_DMA2_ERROR 7
|
||||
#define CONFIG_DEF_IMDMA_ERROR 7
|
||||
#define CONFIG_DEF_PPI1_ERROR 7
|
||||
#define CONFIG_DEF_PPI2_ERROR 7
|
||||
#define CONFIG_DEF_SPORT0_ERROR 7
|
||||
#define CONFIG_DEF_SPORT1_ERROR 7
|
||||
#define CONFIG_DEF_SPI_ERROR 7
|
||||
#define CONFIG_DEF_UART_ERROR 7
|
||||
#define CONFIG_DEF_RESERVED_ERROR 7
|
||||
#define CONFIG_DEF_DMA1_0 8
|
||||
#define CONFIG_DEF_DMA1_1 8
|
||||
#define CONFIG_DEF_DMA1_2 8
|
||||
#define CONFIG_DEF_DMA1_3 8
|
||||
#define CONFIG_DEF_DMA1_4 8
|
||||
#define CONFIG_DEF_DMA1_5 8
|
||||
#define CONFIG_DEF_DMA1_6 8
|
||||
#define CONFIG_DEF_DMA1_7 8
|
||||
#define CONFIG_DEF_DMA1_8 8
|
||||
#define CONFIG_DEF_DMA1_9 8
|
||||
#define CONFIG_DEF_DMA1_10 8
|
||||
#define CONFIG_DEF_DMA1_11 8
|
||||
#define CONFIG_DEF_DMA2_0 9
|
||||
#define CONFIG_DEF_DMA2_1 9
|
||||
#define CONFIG_DEF_DMA2_2 9
|
||||
#define CONFIG_DEF_DMA2_3 9
|
||||
#define CONFIG_DEF_DMA2_4 9
|
||||
#define CONFIG_DEF_DMA2_5 9
|
||||
#define CONFIG_DEF_DMA2_6 9
|
||||
#define CONFIG_DEF_DMA2_7 9
|
||||
#define CONFIG_DEF_DMA2_8 9
|
||||
#define CONFIG_DEF_DMA2_9 9
|
||||
#define CONFIG_DEF_DMA2_10 9
|
||||
#define CONFIG_DEF_DMA2_11 9
|
||||
#define CONFIG_DEF_TIMER0 10
|
||||
#define CONFIG_DEF_TIMER1 10
|
||||
#define CONFIG_DEF_TIMER2 10
|
||||
#define CONFIG_DEF_TIMER3 10
|
||||
#define CONFIG_DEF_TIMER4 10
|
||||
#define CONFIG_DEF_TIMER5 10
|
||||
#define CONFIG_DEF_TIMER6 10
|
||||
#define CONFIG_DEF_TIMER7 10
|
||||
#define CONFIG_DEF_TIMER8 10
|
||||
#define CONFIG_DEF_TIMER9 10
|
||||
#define CONFIG_DEF_TIMER10 10
|
||||
#define CONFIG_DEF_TIMER11 10
|
||||
#define CONFIG_DEF_PROG0_INTA 11
|
||||
#define CONFIG_DEF_PROG0_INTB 11
|
||||
#define CONFIG_DEF_PROG1_INTA 11
|
||||
#define CONFIG_DEF_PROG1_INTB 11
|
||||
#define CONFIG_DEF_PROG2_INTA 11
|
||||
#define CONFIG_DEF_PROG2_INTB 11
|
||||
#define CONFIG_DEF_DMA1_WRRD0 8
|
||||
#define CONFIG_DEF_DMA1_WRRD1 8
|
||||
#define CONFIG_DEF_DMA2_WRRD0 9
|
||||
#define CONFIG_DEF_DMA2_WRRD1 9
|
||||
#define CONFIG_DEF_IMDMA_WRRD0 12
|
||||
#define CONFIG_DEF_IMDMA_WRRD1 12
|
||||
#define CONFIG_DEF_WATCH 13
|
||||
#define CONFIG_DEF_RESERVED_1 7
|
||||
#define CONFIG_DEF_RESERVED_2 7
|
||||
#define CONFIG_DEF_SUPPLE_0 7
|
||||
#define CONFIG_DEF_SUPPLE_1 7
|
||||
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
#define IRQ_DMA1_ERROR_POS 4
|
||||
#define IRQ_DMA2_ERROR_POS 8
|
||||
#define IRQ_IMDMA_ERROR_POS 12
|
||||
#define IRQ_PPI0_ERROR_POS 16
|
||||
#define IRQ_PPI1_ERROR_POS 20
|
||||
#define IRQ_SPORT0_ERROR_POS 24
|
||||
#define IRQ_SPORT1_ERROR_POS 28
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define IRQ_SPI_ERROR_POS 0
|
||||
#define IRQ_UART_ERROR_POS 4
|
||||
#define IRQ_RESERVED_ERROR_POS 8
|
||||
#define IRQ_DMA1_0_POS 12
|
||||
#define IRQ_DMA1_1_POS 16
|
||||
#define IRQ_DMA1_2_POS 20
|
||||
#define IRQ_DMA1_3_POS 24
|
||||
#define IRQ_DMA1_4_POS 28
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define IRQ_DMA1_5_POS 0
|
||||
#define IRQ_DMA1_6_POS 4
|
||||
#define IRQ_DMA1_7_POS 8
|
||||
#define IRQ_DMA1_8_POS 12
|
||||
#define IRQ_DMA1_9_POS 16
|
||||
#define IRQ_DMA1_10_POS 20
|
||||
#define IRQ_DMA1_11_POS 24
|
||||
#define IRQ_DMA2_0_POS 28
|
||||
/* IAR3 BIT FIELDS */
|
||||
#define IRQ_DMA2_1_POS 0
|
||||
#define IRQ_DMA2_2_POS 4
|
||||
#define IRQ_DMA2_3_POS 8
|
||||
#define IRQ_DMA2_4_POS 12
|
||||
#define IRQ_DMA2_5_POS 16
|
||||
#define IRQ_DMA2_6_POS 20
|
||||
#define IRQ_DMA2_7_POS 24
|
||||
#define IRQ_DMA2_8_POS 28
|
||||
/* IAR4 BIT FIELDS */
|
||||
#define IRQ_DMA2_9_POS 0
|
||||
#define IRQ_DMA2_10_POS 4
|
||||
#define IRQ_DMA2_11_POS 8
|
||||
#define IRQ_TIMER0_POS 12
|
||||
#define IRQ_TIMER1_POS 16
|
||||
#define IRQ_TIMER2_POS 20
|
||||
#define IRQ_TIMER3_POS 24
|
||||
#define IRQ_TIMER4_POS 28
|
||||
/* IAR5 BIT FIELDS */
|
||||
#define IRQ_TIMER5_POS 0
|
||||
#define IRQ_TIMER6_POS 4
|
||||
#define IRQ_TIMER7_POS 8
|
||||
#define IRQ_TIMER8_POS 12
|
||||
#define IRQ_TIMER9_POS 16
|
||||
#define IRQ_TIMER10_POS 20
|
||||
#define IRQ_TIMER11_POS 24
|
||||
#define IRQ_PROG0_INTA_POS 28
|
||||
/* IAR6 BIT FIELDS */
|
||||
#define IRQ_PROG0_INTB_POS 0
|
||||
#define IRQ_PROG1_INTA_POS 4
|
||||
#define IRQ_PROG1_INTB_POS 8
|
||||
#define IRQ_PROG2_INTA_POS 12
|
||||
#define IRQ_PROG2_INTB_POS 16
|
||||
#define IRQ_DMA1_WRRD0_POS 20
|
||||
#define IRQ_DMA1_WRRD1_POS 24
|
||||
#define IRQ_DMA2_WRRD0_POS 28
|
||||
/* IAR7 BIT FIELDS */
|
||||
#define IRQ_DMA2_WRRD1_POS 0
|
||||
#define IRQ_IMDMA_WRRD0_POS 4
|
||||
#define IRQ_IMDMA_WRRD1_POS 8
|
||||
#define IRQ_WDTIMER_POS 12
|
||||
#define IRQ_RESERVED_1_POS 16
|
||||
#define IRQ_RESERVED_2_POS 20
|
||||
#define IRQ_SUPPLE_0_POS 24
|
||||
#define IRQ_SUPPLE_1_POS 28
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
#define IRQ_DMA1_ERROR_POS 4
|
||||
#define IRQ_DMA2_ERROR_POS 8
|
||||
#define IRQ_IMDMA_ERROR_POS 12
|
||||
#define IRQ_PPI0_ERROR_POS 16
|
||||
#define IRQ_PPI1_ERROR_POS 20
|
||||
#define IRQ_SPORT0_ERROR_POS 24
|
||||
#define IRQ_SPORT1_ERROR_POS 28
|
||||
|
||||
#endif /* _BF561_IRQ_H_ */
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define IRQ_SPI_ERROR_POS 0
|
||||
#define IRQ_UART_ERROR_POS 4
|
||||
#define IRQ_RESERVED_ERROR_POS 8
|
||||
#define IRQ_DMA1_0_POS 12
|
||||
#define IRQ_DMA1_1_POS 16
|
||||
#define IRQ_DMA1_2_POS 20
|
||||
#define IRQ_DMA1_3_POS 24
|
||||
#define IRQ_DMA1_4_POS 28
|
||||
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define IRQ_DMA1_5_POS 0
|
||||
#define IRQ_DMA1_6_POS 4
|
||||
#define IRQ_DMA1_7_POS 8
|
||||
#define IRQ_DMA1_8_POS 12
|
||||
#define IRQ_DMA1_9_POS 16
|
||||
#define IRQ_DMA1_10_POS 20
|
||||
#define IRQ_DMA1_11_POS 24
|
||||
#define IRQ_DMA2_0_POS 28
|
||||
|
||||
/* IAR3 BIT FIELDS */
|
||||
#define IRQ_DMA2_1_POS 0
|
||||
#define IRQ_DMA2_2_POS 4
|
||||
#define IRQ_DMA2_3_POS 8
|
||||
#define IRQ_DMA2_4_POS 12
|
||||
#define IRQ_DMA2_5_POS 16
|
||||
#define IRQ_DMA2_6_POS 20
|
||||
#define IRQ_DMA2_7_POS 24
|
||||
#define IRQ_DMA2_8_POS 28
|
||||
|
||||
/* IAR4 BIT FIELDS */
|
||||
#define IRQ_DMA2_9_POS 0
|
||||
#define IRQ_DMA2_10_POS 4
|
||||
#define IRQ_DMA2_11_POS 8
|
||||
#define IRQ_TIMER0_POS 12
|
||||
#define IRQ_TIMER1_POS 16
|
||||
#define IRQ_TIMER2_POS 20
|
||||
#define IRQ_TIMER3_POS 24
|
||||
#define IRQ_TIMER4_POS 28
|
||||
|
||||
/* IAR5 BIT FIELDS */
|
||||
#define IRQ_TIMER5_POS 0
|
||||
#define IRQ_TIMER6_POS 4
|
||||
#define IRQ_TIMER7_POS 8
|
||||
#define IRQ_TIMER8_POS 12
|
||||
#define IRQ_TIMER9_POS 16
|
||||
#define IRQ_TIMER10_POS 20
|
||||
#define IRQ_TIMER11_POS 24
|
||||
#define IRQ_PROG0_INTA_POS 28
|
||||
|
||||
/* IAR6 BIT FIELDS */
|
||||
#define IRQ_PROG0_INTB_POS 0
|
||||
#define IRQ_PROG1_INTA_POS 4
|
||||
#define IRQ_PROG1_INTB_POS 8
|
||||
#define IRQ_PROG2_INTA_POS 12
|
||||
#define IRQ_PROG2_INTB_POS 16
|
||||
#define IRQ_DMA1_WRRD0_POS 20
|
||||
#define IRQ_DMA1_WRRD1_POS 24
|
||||
#define IRQ_DMA2_WRRD0_POS 28
|
||||
|
||||
/* IAR7 BIT FIELDS */
|
||||
#define IRQ_DMA2_WRRD1_POS 0
|
||||
#define IRQ_IMDMA_WRRD0_POS 4
|
||||
#define IRQ_IMDMA_WRRD1_POS 8
|
||||
#define IRQ_WDTIMER_POS 12
|
||||
#define IRQ_RESERVED_1_POS 16
|
||||
#define IRQ_RESERVED_2_POS 20
|
||||
#define IRQ_SUPPLE_0_POS 24
|
||||
#define IRQ_SUPPLE_1_POS 28
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue