mirror of https://gitee.com/openkylin/linux.git
powerpc/booke: Add support for new e500mc core
The new e500mc core from Freescale is based on the e500v2 but with the following changes: * Supports only the Enhanced Debug Architecture (DSRR0/1, etc) * Floating Point * No SPE * Supports lwsync * Doorbell Exceptions * Hypervisor * Cache line size is now 64-bytes (e500v1/v2 have a 32-byte cache line) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
bccaea8fe2
commit
3dfa877367
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@ -1522,6 +1522,21 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.machine_check = machine_check_e500,
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.platform = "ppc8548",
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},
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{ /* e500mc */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x80230000,
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.cpu_name = "e500mc",
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/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
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.cpu_features = CPU_FTRS_E500MC,
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.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
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.icache_bsize = 64,
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.dcache_bsize = 64,
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.num_pmcs = 4,
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.oprofile_cpu_type = "ppc/e500", /* xxx - galak, e500mc? */
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.oprofile_type = PPC_OPROFILE_FSL_EMB,
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.machine_check = machine_check_e500,
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.platform = "ppce500mc",
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},
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{ /* default match */
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.pvr_mask = 0x00000000,
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.pvr_value = 0x00000000,
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@ -68,9 +68,13 @@
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#define MCHECK_STACK_BASE mcheckirq_ctx
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#define CRIT_STACK_BASE critirq_ctx
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/* only on e200 for now */
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/* only on e500mc/e200 */
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#define DEBUG_STACK_BASE dbgirq_ctx
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#ifdef CONFIG_PPC_E500MC
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#define DEBUG_SPRG SPRN_SPRG9
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#else
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#define DEBUG_SPRG SPRN_SPRG6W
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#endif
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#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
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@ -304,7 +304,7 @@ skpinv: addi r6,r6,1 /* Increment */
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SET_IVOR(13, DataTLBError);
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SET_IVOR(14, InstructionTLBError);
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SET_IVOR(15, DebugDebug);
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#if defined(CONFIG_E500)
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#if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
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SET_IVOR(15, DebugCrit);
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#endif
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SET_IVOR(32, SPEUnavailable);
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@ -313,6 +313,9 @@ skpinv: addi r6,r6,1 /* Increment */
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#ifndef CONFIG_E200
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SET_IVOR(35, PerformanceMonitor);
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#endif
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#ifdef CONFIG_PPC_E500MC
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SET_IVOR(36, Doorbell);
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#endif
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/* Establish the interrupt vector base */
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lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
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@ -750,10 +753,13 @@ interrupt_base:
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/* Performance Monitor */
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EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
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#ifdef CONFIG_PPC_E500MC
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EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_EE)
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#endif
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/* Debug Interrupt */
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DEBUG_DEBUG_EXCEPTION
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#if defined(CONFIG_E500)
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#if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
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DEBUG_CRIT_EXCEPTION
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#endif
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@ -95,6 +95,11 @@ config E500
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select FSL_EMB_PERFMON
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bool
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config PPC_E500MC
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bool "e500mc Support"
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select PPC_FPU
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depends on E500
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config PPC_FPU
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bool
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default y if PPC64
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@ -157,7 +162,7 @@ config ALTIVEC
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config SPE
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bool "SPE Support"
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depends on E200 || E500
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depends on E200 || (E500 && !PPC_E500MC)
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default y
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---help---
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This option enables kernel support for the Signal Processing
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@ -8,6 +8,9 @@
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#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
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#define L1_CACHE_SHIFT 4
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#define MAX_COPY_PREFETCH 1
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#elif defined(CONFIG_PPC_E500MC)
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#define L1_CACHE_SHIFT 6
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#define MAX_COPY_PREFETCH 4
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#elif defined(CONFIG_PPC32)
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#define L1_CACHE_SHIFT 5
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#define MAX_COPY_PREFETCH 4
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@ -351,6 +351,8 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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CPU_FTR_NODSISRALIGN)
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#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
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CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
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#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS | \
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CPU_FTR_NODSISRALIGN)
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#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
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/* 64-bit CPUs */
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@ -421,7 +423,7 @@ enum {
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CPU_FTRS_E200 |
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#endif
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#ifdef CONFIG_E500
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CPU_FTRS_E500 | CPU_FTRS_E500_2 |
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CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
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#endif
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0,
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};
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@ -461,7 +463,7 @@ enum {
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CPU_FTRS_E200 &
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#endif
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#ifdef CONFIG_E500
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CPU_FTRS_E500 & CPU_FTRS_E500_2 &
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CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
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#endif
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CPU_FTRS_POSSIBLE,
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};
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@ -4,7 +4,7 @@
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#include <linux/stringify.h>
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#ifdef __powerpc64__
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#if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC)
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#define __SUBARCH_HAS_LWSYNC
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#endif
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