mirror of https://gitee.com/openkylin/linux.git
clk: renesas: rcar-gen2: Improve arithmetic divisions
- Use div64_ul() instead of div_u64() if the divisor is unsigned long, to avoid truncation to 32-bit on 64-bit platforms, - Prefer ULL constant suffixes over casts to u64, - Prioritize multiplication over division, to increase accuracy. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20190830134515.11925-2-geert+renesas@glider.be
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@ -72,10 +72,10 @@ static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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if (!prate)
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if (!prate)
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prate = 1;
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prate = 1;
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mult = div_u64((u64)rate * 32, prate);
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mult = div64_ul(rate * 32ULL, prate);
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mult = clamp(mult, 1U, 32U);
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mult = clamp(mult, 1U, 32U);
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return *parent_rate / 32 * mult;
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return div_u64((u64)*parent_rate * mult, 32);
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}
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}
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static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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@ -86,7 +86,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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u32 val, kick;
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u32 val, kick;
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unsigned int i;
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unsigned int i;
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mult = div_u64((u64)rate * 32, parent_rate);
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mult = div64_ul(rate * 32ULL, parent_rate);
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mult = clamp(mult, 1U, 32U);
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mult = clamp(mult, 1U, 32U);
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if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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