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drm/amd/pp: Rename enable_per_cu_power_gating to powergate_gfx 

keep consistent with powergate_uvd/vce/mmhub

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-06-05 11:28:03 +08:00 committed by Alex Deucher
parent a8da8ff333
commit 3eb6e4795d
5 changed files with 7 additions and 7 deletions
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6
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
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@ -236,13 +236,13 @@ static int pp_set_powergating_state(void *handle,
pr_err("gfx off control failed!\n"); pr_err("gfx off control failed!\n");
} }
if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) { if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
pr_debug("%s was not implemented.\n", __func__); pr_info("%s was not implemented.\n", __func__);
return 0; return 0;
} }
/* Enable/disable GFX per cu powergating through SMU */ /* Enable/disable GFX per cu powergating through SMU */
return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr, return hwmgr->hwmgr_func->powergate_gfx(hwmgr,
state == AMD_PG_STATE_GATE); state == AMD_PG_STATE_GATE);
} }

2
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
View File

@ -416,7 +416,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
* Powerplay will only control the static per CU Power Gating. * Powerplay will only control the static per CU Power Gating.
* Dynamic per CU Power Gating will be done in gfx. * Dynamic per CU Power Gating will be done in gfx.
*/ */
int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable) int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable)
{ {
struct amdgpu_device *adev = hwmgr->adev; struct amdgpu_device *adev = hwmgr->adev;

2
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
View File

@ -33,6 +33,6 @@ int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr); int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
const uint32_t *msg_id); const uint32_t *msg_id);
int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable); int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable);
#endif #endif

2
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
View File

@ -5044,7 +5044,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.get_fan_control_mode = smu7_get_fan_control_mode, .get_fan_control_mode = smu7_get_fan_control_mode,
.force_clock_level = smu7_force_clock_level, .force_clock_level = smu7_force_clock_level,
.print_clock_levels = smu7_print_clock_levels, .print_clock_levels = smu7_print_clock_levels,
.enable_per_cu_power_gating = smu7_enable_per_cu_power_gating, .powergate_gfx = smu7_powergate_gfx,
.get_sclk_od = smu7_get_sclk_od, .get_sclk_od = smu7_get_sclk_od,
.set_sclk_od = smu7_set_sclk_od, .set_sclk_od = smu7_set_sclk_od,
.get_mclk_od = smu7_get_mclk_od, .get_mclk_od = smu7_get_mclk_od,

2
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
View File

@ -302,7 +302,7 @@ struct pp_hwmgr_func {
int (*power_off_asic)(struct pp_hwmgr *hwmgr); int (*power_off_asic)(struct pp_hwmgr *hwmgr);
int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf); int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable); int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
int (*get_sclk_od)(struct pp_hwmgr *hwmgr); int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
int (*get_mclk_od)(struct pp_hwmgr *hwmgr); int (*get_mclk_od)(struct pp_hwmgr *hwmgr);