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drm/i915: use FPGA_DBG for the "unclaimed register" checks 

We plan to treat GEN7_ERR_INT as an interrupt, so use this register
for the checks inside I915_WRITE. This way we can have the best of
both worlds: the error message with a register address and the

V2: Split in 2 patches: one for the macro, one for changing the
register, as requested by Ben.
V3: Rebase.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Paulo Zanoni 2013-02-18 19:00:21 -03:00 committed by Daniel Vetter
parent 115bc2de52
commit 3f1e109a8b
2 changed files with 7 additions and 4 deletions
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8
drivers/gpu/drm/i915/i915_drv.c
View File

@ -1133,10 +1133,10 @@ static void
hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
{ {
if (IS_HASWELL(dev_priv->dev) && if (IS_HASWELL(dev_priv->dev) &&
(I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
DRM_ERROR("Unknown unclaimed register before writing to %x\n", DRM_ERROR("Unknown unclaimed register before writing to %x\n",
reg); reg);
I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
} }
} }
@ -1144,9 +1144,9 @@ static void
hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
{ {
if (IS_HASWELL(dev_priv->dev) && if (IS_HASWELL(dev_priv->dev) &&
(I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
DRM_ERROR("Unclaimed write to %x\n", reg); DRM_ERROR("Unclaimed write to %x\n", reg);
writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
} }
} }

3
drivers/gpu/drm/i915/i915_reg.h
View File

@ -522,6 +522,9 @@
#define GEN7_ERR_INT 0x44040 #define GEN7_ERR_INT 0x44040
#define ERR_INT_MMIO_UNCLAIMED (1<<13) #define ERR_INT_MMIO_UNCLAIMED (1<<13)
#define FPGA_DBG 0x42300
#define FPGA_DBG_RM_NOCLAIM (1<<31)
#define DERRMR 0x44050 #define DERRMR 0x44050
/* GM45+ chicken bits -- debug workaround bits that may be required /* GM45+ chicken bits -- debug workaround bits that may be required