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net: dsa: felix: clarify the intention of writes to MII_BMCR
The driver appears to write to BMCR_SPEED and BMCR_DUPLEX, fields which are read-only, since they are actually configured through the vendor-specific IF_MODE (0x14) register. But the reason we're writing back the read-only values of MII_BMCR is to alter these writable fields: BMCR_RESET BMCR_LOOPBACK BMCR_ANENABLE BMCR_PDOWN BMCR_ISOLATE BMCR_ANRESTART In particular, the only field which is really relevant to this driver is BMCR_ANENABLE. Clarify that intention by spelling it out, using phy_set_bits and phy_clear_bits. The driver also made a few writes to BMCR_RESET and BMCR_ANRESTART which are unnecessary and may temporarily disrupt the link to the PHY. Remove them. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -815,7 +815,7 @@ static void vsc9959_pcs_init_sgmii(struct phy_device *pcs,
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phy_write(pcs, ENETC_PCS_LINK_TIMER2,
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ENETC_PCS_LINK_TIMER2_VAL);
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phy_write(pcs, MII_BMCR, BMCR_ANRESTART | BMCR_ANENABLE);
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phy_set_bits(pcs, MII_BMCR, BMCR_ANENABLE);
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} else {
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int speed;
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@ -845,10 +845,7 @@ static void vsc9959_pcs_init_sgmii(struct phy_device *pcs,
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ENETC_PCS_IF_MODE_SGMII_EN |
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ENETC_PCS_IF_MODE_SGMII_SPEED(speed));
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/* Yes, not a mistake: speed is given by IF_MODE. */
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phy_write(pcs, MII_BMCR, BMCR_RESET |
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BMCR_SPEED1000 |
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BMCR_FULLDPLX);
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phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
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}
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}
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@ -882,9 +879,7 @@ static void vsc9959_pcs_init_2500basex(struct phy_device *pcs,
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ENETC_PCS_IF_MODE_SGMII_EN |
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ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500));
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phy_write(pcs, MII_BMCR, BMCR_SPEED1000 |
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BMCR_FULLDPLX |
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BMCR_RESET);
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phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
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}
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static void vsc9959_pcs_init_usxgmii(struct phy_device *pcs,
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