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ARM: dts: r8a7779: Remove unnecessary clock-output-names properties 

* Fixed rate and fixed factor clocks do not require an
  clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
  optional") Renesas div6 clocks do not require a clock-output-names
  property.

In the above cases there is only one clock output and its name is taken
from that of the clock node.  Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Simon Horman 2016-03-18 08:15:34 +09:00
parent 452fc89994
commit 3f6dba702c
1 changed files with 5 additions and 10 deletions
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15
arch/arm/boot/dts/r8a7779.dtsi
View File

@ -445,12 +445,11 @@ clocks {
ranges; ranges;
/* External root clock */ /* External root clock */
extal_clk: extal_clk { extal_clk: extal {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
/* This value must be overriden by the board. */ /* This value must be overriden by the board. */
clock-frequency = <0>; clock-frequency = <0>;
clock-output-names = "extal";
}; };
/* External SCIF clock */ /* External SCIF clock */
@ -474,37 +473,33 @@ cpg_clocks: clocks@ffc80000 {
}; };
/* Fixed factor clocks */ /* Fixed factor clocks */
i_clk: i_clk { i_clk: i {
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>; clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>; #clock-cells = <0>;
clock-div = <2>; clock-div = <2>;
clock-mult = <1>; clock-mult = <1>;
clock-output-names = "i";
}; };
s3_clk: s3_clk { s3_clk: s3 {
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>; clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>; #clock-cells = <0>;
clock-div = <8>; clock-div = <8>;
clock-mult = <1>; clock-mult = <1>;
clock-output-names = "s3";
}; };
s4_clk: s4_clk { s4_clk: s4 {
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>; clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>; #clock-cells = <0>;
clock-div = <16>; clock-div = <16>;
clock-mult = <1>; clock-mult = <1>;
clock-output-names = "s4";
}; };
g_clk: g_clk { g_clk: g {
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>; clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>; #clock-cells = <0>;
clock-div = <24>; clock-div = <24>;
clock-mult = <1>; clock-mult = <1>;
clock-output-names = "g";
}; };
/* Gate clocks */ /* Gate clocks */