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arm64: KVM: define 32bit specific registers
Define the 32bit specific registers (SPSRs, cp15...). Most CPU registers are directly mapped to a 64bit register (r0->x0...). Only the SPSRs have separate registers. cp15 registers are also mapped into their 64bit counterpart in most cases. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -42,7 +42,43 @@
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#define TPIDR_EL1 18 /* Thread ID, Privileged */
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#define AMAIR_EL1 19 /* Aux Memory Attribute Indirection Register */
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#define CNTKCTL_EL1 20 /* Timer Control Register (EL1) */
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#define NR_SYS_REGS 21
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/* 32bit specific registers. Keep them at the end of the range */
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#define DACR32_EL2 21 /* Domain Access Control Register */
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#define IFSR32_EL2 22 /* Instruction Fault Status Register */
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#define FPEXC32_EL2 23 /* Floating-Point Exception Control Register */
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#define DBGVCR32_EL2 24 /* Debug Vector Catch Register */
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#define TEECR32_EL1 25 /* ThumbEE Configuration Register */
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#define TEEHBR32_EL1 26 /* ThumbEE Handler Base Register */
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#define NR_SYS_REGS 27
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/* 32bit mapping */
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#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
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#define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
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#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
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#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
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#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
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#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
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#define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
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#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
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#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
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#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
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#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
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#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
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#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
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#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
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#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
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#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
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#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
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#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
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#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
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#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
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#define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
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#define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
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#define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
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#define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
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#define c10_AMAIR (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
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#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
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#define NR_CP15_REGS (NR_SYS_REGS * 2)
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#define ARM_EXCEPTION_IRQ 0
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#define ARM_EXCEPTION_TRAP 1
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@ -84,7 +84,10 @@ struct kvm_vcpu_fault_info {
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struct kvm_cpu_context {
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struct kvm_regs gp_regs;
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u64 sys_regs[NR_SYS_REGS];
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union {
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u64 sys_regs[NR_SYS_REGS];
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u32 cp15[NR_CP15_REGS];
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};
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};
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typedef struct kvm_cpu_context kvm_cpu_context_t;
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@ -23,7 +23,12 @@
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#define __ARM_KVM_H__
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#define KVM_SPSR_EL1 0
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#define KVM_NR_SPSR 1
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#define KVM_SPSR_SVC KVM_SPSR_EL1
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#define KVM_SPSR_ABT 1
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#define KVM_SPSR_UND 2
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#define KVM_SPSR_IRQ 3
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#define KVM_SPSR_FIQ 4
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#define KVM_NR_SPSR 5
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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