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mtd: pxa3xx_nand: mtd scan id process could be defined by driver itself
Different NAND driver may require its unique detection. For pxa3xx_nand, it use its self id database to get the necessary info. Signed-off-by: Lei Wen <leiwen@marvell.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Lei Wen
David Woodhouse
parent
4eb2da8994
commit
401e67e225
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@ -123,6 +123,7 @@ enum {
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struct pxa3xx_nand_info {
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struct nand_chip nand_chip;
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struct nand_hw_control controller;
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struct platform_device *pdev;
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struct pxa3xx_nand_cmdset *cmdset;
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@ -157,6 +158,7 @@ struct pxa3xx_nand_info {
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int use_ecc; /* use HW ECC ? */
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int use_dma; /* use DMA ? */
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int is_ready;
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unsigned int page_size; /* page size of attached chip */
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unsigned int data_size; /* data size in FIFO */
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@ -223,6 +225,8 @@ static struct pxa3xx_nand_flash builtin_flash_types[] = {
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/* Define a default flash type setting serve as flash detecting only */
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#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
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const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
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#define NDTR0_tCH(c) (min((c), 7) << 19)
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#define NDTR0_tCS(c) (min((c), 7) << 16)
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#define NDTR0_tWH(c) (min((c), 7) << 11)
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@ -437,8 +441,10 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
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info->state = STATE_CMD_DONE;
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is_completed = 1;
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}
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if (status & NDSR_FLASH_RDY)
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if (status & NDSR_FLASH_RDY) {
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info->is_ready = 1;
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info->state = STATE_READY;
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}
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if (status & NDSR_WRCMDREQ) {
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nand_writel(info, NDSR, NDSR_WRCMDREQ);
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@ -483,10 +489,11 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
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exec_cmd = 1;
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/* reset data and oob column point to handle data */
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info->buf_start = 0;
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info->buf_count = 0;
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info->buf_start = 0;
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info->buf_count = 0;
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info->oob_size = 0;
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info->use_ecc = 0;
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info->is_ready = 0;
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info->retcode = ERR_NONE;
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switch (command) {
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@ -849,42 +856,6 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
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return 0;
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}
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static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
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const struct pxa3xx_nand_platform_data *pdata)
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{
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const struct pxa3xx_nand_flash *f;
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uint32_t id = -1;
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int i;
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if (pdata->keep_config)
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if (pxa3xx_nand_detect_config(info) == 0)
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return 0;
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/* we use default timing to detect id */
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f = DEFAULT_FLASH_TYPE;
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pxa3xx_nand_config_flash(info, f);
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pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
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id = *((uint16_t *)(info->data_buff));
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for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
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/* we first choose the flash definition from platfrom */
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if (i < pdata->num_flash)
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f = pdata->flash + i;
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else
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f = &builtin_flash_types[i - pdata->num_flash + 1];
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if (f->chip_id == id) {
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dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
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pxa3xx_nand_config_flash(info, f);
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return 0;
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}
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}
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dev_warn(&info->pdev->dev,
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"failed to detect configured nand flash; found %04x instead of\n",
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id);
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return -ENODEV;
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}
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/* the maximum possible buffer size for large page with OOB data
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* is: 2048 + 64 = 2112 bytes, allocate a page here for both the
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* data buffer and the DMA descriptor
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@ -926,57 +897,110 @@ static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
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return 0;
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}
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static struct nand_ecclayout hw_smallpage_ecclayout = {
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.eccbytes = 6,
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.eccpos = {8, 9, 10, 11, 12, 13 },
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.oobfree = { {2, 6} }
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};
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static struct nand_ecclayout hw_largepage_ecclayout = {
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.eccbytes = 24,
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.eccpos = {
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40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55,
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56, 57, 58, 59, 60, 61, 62, 63},
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.oobfree = { {2, 38} }
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};
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static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
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struct pxa3xx_nand_info *info)
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static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
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{
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struct nand_chip *this = &info->nand_chip;
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struct mtd_info *mtd = info->mtd;
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struct nand_chip *chip = mtd->priv;
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this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;
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this->options |= NAND_NO_AUTOINCR;
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this->waitfunc = pxa3xx_nand_waitfunc;
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this->select_chip = pxa3xx_nand_select_chip;
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this->dev_ready = pxa3xx_nand_dev_ready;
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this->cmdfunc = pxa3xx_nand_cmdfunc;
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this->ecc.read_page = pxa3xx_nand_read_page_hwecc;
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this->ecc.write_page = pxa3xx_nand_write_page_hwecc;
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this->read_word = pxa3xx_nand_read_word;
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this->read_byte = pxa3xx_nand_read_byte;
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this->read_buf = pxa3xx_nand_read_buf;
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this->write_buf = pxa3xx_nand_write_buf;
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this->verify_buf = pxa3xx_nand_verify_buf;
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this->ecc.mode = NAND_ECC_HW;
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this->ecc.size = info->page_size;
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if (info->page_size == 2048)
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this->ecc.layout = &hw_largepage_ecclayout;
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/* use the common timing to make a try */
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pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
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chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
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if (info->is_ready)
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return 1;
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else
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this->ecc.layout = &hw_smallpage_ecclayout;
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return 0;
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}
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this->chip_delay = 25;
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static int pxa3xx_nand_scan(struct mtd_info *mtd)
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{
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struct pxa3xx_nand_info *info = mtd->priv;
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struct platform_device *pdev = info->pdev;
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struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
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const struct pxa3xx_nand_flash *f = NULL;
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struct nand_chip *chip = mtd->priv;
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uint32_t id = -1;
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int i, ret, num;
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if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
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return 0;
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ret = pxa3xx_nand_sensing(info);
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if (!ret) {
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kfree(mtd);
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info->mtd = NULL;
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printk(KERN_INFO "There is no nand chip on cs 0!\n");
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return -EINVAL;
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}
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chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
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id = *((uint16_t *)(info->data_buff));
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if (id != 0)
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printk(KERN_INFO "Detect a flash id %x\n", id);
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else {
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kfree(mtd);
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info->mtd = NULL;
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printk(KERN_WARNING "Read out ID 0, potential timing set wrong!!\n");
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return -EINVAL;
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}
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num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
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for (i = 0; i < num; i++) {
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if (i < pdata->num_flash)
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f = pdata->flash + i;
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else
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f = &builtin_flash_types[i - pdata->num_flash + 1];
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/* find the chip in default list */
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if (f->chip_id == id) {
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pxa3xx_nand_config_flash(info, f);
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mtd->writesize = f->page_size;
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mtd->writesize_shift = ffs(mtd->writesize) - 1;
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mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
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mtd->oobsize = mtd->writesize / 32;
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mtd->erasesize = f->page_size * f->page_per_block;
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mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
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mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
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mtd->name = mtd_names[0];
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break;
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}
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}
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if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash)) {
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kfree(mtd);
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info->mtd = NULL;
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printk(KERN_ERR "ERROR!! flash not defined!!!\n");
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return -EINVAL;
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}
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.size = f->page_size;
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chip->chipsize = (uint64_t)f->num_blocks * f->page_per_block
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* f->page_size;
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mtd->size = chip->chipsize;
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/* Calculate the address shift from the page size */
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chip->page_shift = ffs(mtd->writesize) - 1;
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chip->pagemask = mtd_div_by_ws(chip->chipsize, mtd) - 1;
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chip->numchips = 1;
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chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
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chip->bbt_erase_shift = chip->phys_erase_shift;
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chip->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16 : 0;
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chip->options |= NAND_NO_AUTOINCR;
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chip->options |= NAND_NO_READRDY;
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return nand_scan_tail(mtd);
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}
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static
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struct pxa3xx_nand_info *alloc_nand_resource(struct platform_device *pdev)
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{
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struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
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struct pxa3xx_nand_info *info;
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struct nand_chip *chip;
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struct mtd_info *mtd;
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struct resource *r;
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int ret, irq;
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@ -989,12 +1013,27 @@ struct pxa3xx_nand_info *alloc_nand_resource(struct platform_device *pdev)
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}
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info = (struct pxa3xx_nand_info *)(&mtd[1]);
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chip = (struct nand_chip *)(&mtd[1]);
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info->pdev = pdev;
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mtd->priv = info;
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info->mtd = mtd;
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mtd->priv = info;
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mtd->owner = THIS_MODULE;
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chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
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chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
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chip->controller = &info->controller;
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chip->waitfunc = pxa3xx_nand_waitfunc;
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chip->select_chip = pxa3xx_nand_select_chip;
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chip->dev_ready = pxa3xx_nand_dev_ready;
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chip->cmdfunc = pxa3xx_nand_cmdfunc;
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chip->read_word = pxa3xx_nand_read_word;
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chip->read_byte = pxa3xx_nand_read_byte;
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chip->read_buf = pxa3xx_nand_read_buf;
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chip->write_buf = pxa3xx_nand_write_buf;
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chip->verify_buf = pxa3xx_nand_verify_buf;
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spin_lock_init(&chip->controller->lock);
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init_waitqueue_head(&chip->controller->wq);
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info->clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(info->clk)) {
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dev_err(&pdev->dev, "failed to get nand clock\n");
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@ -1062,21 +1101,12 @@ struct pxa3xx_nand_info *alloc_nand_resource(struct platform_device *pdev)
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goto fail_free_buf;
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}
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ret = pxa3xx_nand_detect_flash(info, pdata);
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if (ret) {
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dev_err(&pdev->dev, "failed to detect flash\n");
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ret = -ENODEV;
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goto fail_free_irq;
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}
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pxa3xx_nand_init_mtd(mtd, info);
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platform_set_drvdata(pdev, info);
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return info;
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fail_free_irq:
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free_irq(irq, info);
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fail_free_buf:
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free_irq(irq, info);
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if (use_dma) {
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pxa_free_dma(info->data_dma_ch);
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dma_free_coherent(&pdev->dev, info->data_buff_size,
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@ -1146,7 +1176,7 @@ static int pxa3xx_nand_probe(struct platform_device *pdev)
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if (info == NULL)
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return -ENOMEM;
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if (nand_scan(info->mtd, 1)) {
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if (pxa3xx_nand_scan(info->mtd)) {
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dev_err(&pdev->dev, "failed to scan nand\n");
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pxa3xx_nand_remove(pdev);
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return -ENODEV;
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