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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull more MIPS updates from Ralf Baechle:
 "This is the secondnd batch of MIPS patches for 4.7. Summary:

  CPS:
   - Copy EVA configuration when starting secondary VPs.

  EIC:
   - Clear Status IPL.

  Lasat:
   - Fix a few off by one bugs.

  lib:
   - Mark intrinsics notrace.  Not only are the intrinsics
     uninteresting, it would cause infinite recursion.

  MAINTAINERS:
   - Add file patterns for MIPS BRCM device tree bindings.
   - Add file patterns for mips device tree bindings.

  MT7628:
   - Fix MT7628 pinmux typos.
   - wled_an pinmux gpio.
   - EPHY LEDs pinmux support.

  Pistachio:
   - Enable KASLR

  VDSO:
   - Build microMIPS VDSO for microMIPS kernels.
   - Fix aliasing warning by building with `-fno-strict-aliasing' for
     debugging but also tracing them might result in recursion.

  Misc:
   - Add missing FROZEN hotplug notifier transitions.
   - Fix clk binding example for varioius PIC32 devices.
   - Fix cpu interrupt controller node-names in the DT files.
   - Fix XPA CPU feature separation.
   - Fix write_gc0_* macros when writing zero.
   - Add inline asm encoding helpers.
   - Add missing VZ accessor microMIPS encodings.
   - Fix little endian microMIPS MSA encodings.
   - Add 64-bit HTW fields and fix its configuration.
   - Fix sigreturn via VDSO on microMIPS kernel.
   - Lots of typo fixes.
   - Add definitions of SegCtl registers and use them"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (49 commits)
  MIPS: Add missing FROZEN hotplug notifier transitions
  MIPS: Build microMIPS VDSO for microMIPS kernels
  MIPS: Fix sigreturn via VDSO on microMIPS kernel
  MIPS: devicetree: fix cpu interrupt controller node-names
  MIPS: VDSO: Build with `-fno-strict-aliasing'
  MIPS: Pistachio: Enable KASLR
  MIPS: lib: Mark intrinsics notrace
  MIPS: Fix 64-bit HTW configuration
  MIPS: Add 64-bit HTW fields
  MAINTAINERS: Add file patterns for mips device tree bindings
  MAINTAINERS: Add file patterns for mips brcm device tree bindings
  MIPS: Simplify DSP instruction encoding macros
  MIPS: Add missing tlbinvf/XPA microMIPS encodings
  MIPS: Fix little endian microMIPS MSA encodings
  MIPS: Add missing VZ accessor microMIPS encodings
  MIPS: Add inline asm encoding helpers
  MIPS: Spelling fix lets -> let's
  MIPS: VR41xx: Fix typo
  MIPS: oprofile: Fix typo
  MIPS: math-emu: Fix typo
  ...
This commit is contained in:
Linus Torvalds 2016-05-28 16:41:39 -07:00
parent d66492bce1 a8c5ddf08f
commit 4029632c34
67 changed files with 376 additions and 261 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
View File

@ -33,7 +33,7 @@ gpio0: gpio0@1f860000 {
gpio-controller; gpio-controller;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
clocks = <&PBCLK4>; clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <0>; microchip,gpio-bank = <0>;
gpio-ranges = <&pic32_pinctrl 0 0 16>; gpio-ranges = <&pic32_pinctrl 0 0 16>;
}; };

2
Documentation/devicetree/bindings/mips/cpu_irq.txt
View File

@ -13,7 +13,7 @@ Required properties:
- compatible : Should be "mti,cpu-interrupt-controller" - compatible : Should be "mti,cpu-interrupt-controller"
Example devicetree: Example devicetree:
cpu-irq: cpu-irq@0 { cpu-irq: cpu-irq {
#address-cells = <0>; #address-cells = <0>;
interrupt-controller; interrupt-controller;

2
Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt
View File

@ -20,7 +20,7 @@ Example:
compatible = "microchip,pic32mzda-sdhci"; compatible = "microchip,pic32mzda-sdhci";
reg = <0x1f8ec000 0x100>; reg = <0x1f8ec000 0x100>;
interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&REFCLKO4>, <&PBCLK5>; clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>;
clock-names = "base_clk", "sys_clk"; clock-names = "base_clk", "sys_clk";
bus-width = <4>; bus-width = <4>;
cap-sd-highspeed; cap-sd-highspeed;

2
Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
View File

@ -34,7 +34,7 @@ pic32_pinctrl: pinctrl@1f801400{
#size-cells = <1>; #size-cells = <1>;
compatible = "microchip,pic32mzda-pinctrl"; compatible = "microchip,pic32mzda-pinctrl";
reg = <0x1f801400 0x400>; reg = <0x1f801400 0x400>;
clocks = <&PBCLK1>; clocks = <&rootclk PB1CLK>;
pinctrl_uart2: pinctrl_uart2 { pinctrl_uart2: pinctrl_uart2 {
uart2-tx { uart2-tx {

2
Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt
View File

@ -20,7 +20,7 @@ Example:
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
<113 IRQ_TYPE_LEVEL_HIGH>, <113 IRQ_TYPE_LEVEL_HIGH>,
<114 IRQ_TYPE_LEVEL_HIGH>; <114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&PBCLK2>; clocks = <&rootclk PB2CLK>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1 pinctrl-0 = <&pinctrl_uart1
&pinctrl_uart1_cts &pinctrl_uart1_cts

4
Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt
View File

@ -8,12 +8,12 @@ Required properties:
- compatible: must be "microchip,pic32mzda-dmt". - compatible: must be "microchip,pic32mzda-dmt".
- reg: physical base address of the controller and length of memory mapped - reg: physical base address of the controller and length of memory mapped
region. region.
- clocks: phandle of parent clock (should be &PBCLK7). - clocks: phandle of source clk. Should be <&rootclk PB7CLK>.
Example: Example:
watchdog@1f800a00 { watchdog@1f800a00 {
compatible = "microchip,pic32mzda-dmt"; compatible = "microchip,pic32mzda-dmt";
reg = <0x1f800a00 0x80>; reg = <0x1f800a00 0x80>;
clocks = <&PBCLK7>; clocks = <&rootclk PB7CLK>;
}; };

4
Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
View File

@ -7,12 +7,12 @@ Required properties:
- compatible: must be "microchip,pic32mzda-wdt". - compatible: must be "microchip,pic32mzda-wdt".
- reg: physical base address of the controller and length of memory mapped - reg: physical base address of the controller and length of memory mapped
region. region.
- clocks: phandle of source clk. should be <&LPRC> clk. - clocks: phandle of source clk. Should be <&rootclk LPRCCLK>.
Example: Example:
watchdog@1f800800 { watchdog@1f800800 {
compatible = "microchip,pic32mzda-wdt"; compatible = "microchip,pic32mzda-wdt";
reg = <0x1f800800 0x200>; reg = <0x1f800800 0x200>;
clocks = <&LPRC>; clocks = <&rootclk LPRCCLK>;
}; };

2
MAINTAINERS
View File

@ -2505,6 +2505,7 @@ M: Hauke Mehrtens <hauke@hauke-m.de>
M: Rafał Miłecki <zajec5@gmail.com> M: Rafał Miłecki <zajec5@gmail.com>
L: linux-mips@linux-mips.org L: linux-mips@linux-mips.org
S: Maintained S: Maintained
F: Documentation/devicetree/bindings/mips/brcm/
F: arch/mips/bcm47xx/* F: arch/mips/bcm47xx/*
F: arch/mips/include/asm/mach-bcm47xx/* F: arch/mips/include/asm/mach-bcm47xx/*
@ -7521,6 +7522,7 @@ W: http://www.linux-mips.org/
T: git git://git.linux-mips.org/pub/scm/ralf/linux.git T: git git://git.linux-mips.org/pub/scm/ralf/linux.git
Q: http://patchwork.linux-mips.org/project/linux-mips/list/ Q: http://patchwork.linux-mips.org/project/linux-mips/list/
S: Supported S: Supported
F: Documentation/devicetree/bindings/mips/
F: Documentation/mips/ F: Documentation/mips/
F: arch/mips/ F: arch/mips/

1
arch/mips/Kconfig
View File

@ -398,6 +398,7 @@ config MACH_PISTACHIO
select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MIPS_CPS select SYS_SUPPORTS_MIPS_CPS
select SYS_SUPPORTS_MULTITHREADING select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_RELOCATABLE
select SYS_SUPPORTS_ZBOOT select SYS_SUPPORTS_ZBOOT
select SYS_HAS_EARLY_PRINTK select SYS_HAS_EARLY_PRINTK
select USE_GENERIC_EARLY_PRINTK_8250 select USE_GENERIC_EARLY_PRINTK_8250

2
arch/mips/boot/dts/ingenic/jz4740.dtsi
View File

@ -5,7 +5,7 @@ / {
#size-cells = <1>; #size-cells = <1>;
compatible = "ingenic,jz4740"; compatible = "ingenic,jz4740";
cpuintc: interrupt-controller@0 { cpuintc: interrupt-controller {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;

2
arch/mips/boot/dts/ralink/mt7620a.dtsi
View File

@ -9,7 +9,7 @@ cpu@0 {
}; };
}; };
cpuintc: cpuintc@0 { cpuintc: cpuintc {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;

2
arch/mips/boot/dts/ralink/rt2880.dtsi
View File

@ -9,7 +9,7 @@ cpu@0 {
}; };
}; };
cpuintc: cpuintc@0 { cpuintc: cpuintc {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;

2
arch/mips/boot/dts/ralink/rt3050.dtsi
View File

@ -9,7 +9,7 @@ cpu@0 {
}; };
}; };
cpuintc: cpuintc@0 { cpuintc: cpuintc {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;

2
arch/mips/boot/dts/ralink/rt3883.dtsi
View File

@ -9,7 +9,7 @@ cpu@0 {
}; };
}; };
cpuintc: cpuintc@0 { cpuintc: cpuintc {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;

2
arch/mips/boot/dts/xilfpga/nexys4ddr.dts
View File

@ -10,7 +10,7 @@ memory {
reg = <0x0 0x08000000>; reg = <0x0 0x08000000>;
}; };
cpuintc: interrupt-controller@0 { cpuintc: interrupt-controller {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
interrupt-controller; interrupt-controller;

2
arch/mips/cavium-octeon/smp.c
View File

@ -384,7 +384,7 @@ static int octeon_cpu_callback(struct notifier_block *nfb,
{ {
unsigned int cpu = (unsigned long)hcpu; unsigned int cpu = (unsigned long)hcpu;
switch (action) { switch (action & ~CPU_TASKS_FROZEN) {
case CPU_UP_PREPARE: case CPU_UP_PREPARE:
octeon_update_boot_vector(cpu); octeon_update_boot_vector(cpu);
break; break;

99
arch/mips/include/asm/asmmacro.h
View File

@ -19,6 +19,28 @@
#include <asm/asmmacro-64.h> #include <asm/asmmacro-64.h>
#endif #endif
/*
* Helper macros for generating raw instruction encodings.
*/
#ifdef CONFIG_CPU_MICROMIPS
.macro insn32_if_mm enc
.insn
.hword ((\enc) >> 16)
.hword ((\enc) & 0xffff)
.endm
.macro insn_if_mips enc
.endm
#else
.macro insn32_if_mm enc
.endm
.macro insn_if_mips enc
.insn
.word (\enc)
.endm
#endif
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
.macro local_irq_enable reg=t0 .macro local_irq_enable reg=t0
ei ei
@ -341,38 +363,6 @@
.endm .endm
#else #else
#ifdef CONFIG_CPU_MICROMIPS
#define CFC_MSA_INSN 0x587e0056
#define CTC_MSA_INSN 0x583e0816
#define LDB_MSA_INSN 0x58000807
#define LDH_MSA_INSN 0x58000817
#define LDW_MSA_INSN 0x58000827
#define LDD_MSA_INSN 0x58000837
#define STB_MSA_INSN 0x5800080f
#define STH_MSA_INSN 0x5800081f
#define STW_MSA_INSN 0x5800082f
#define STD_MSA_INSN 0x5800083f
#define COPY_SW_MSA_INSN 0x58b00056
#define COPY_SD_MSA_INSN 0x58b80056
#define INSERT_W_MSA_INSN 0x59300816
#define INSERT_D_MSA_INSN 0x59380816
#else
#define CFC_MSA_INSN 0x787e0059
#define CTC_MSA_INSN 0x783e0819
#define LDB_MSA_INSN 0x78000820
#define LDH_MSA_INSN 0x78000821
#define LDW_MSA_INSN 0x78000822
#define LDD_MSA_INSN 0x78000823
#define STB_MSA_INSN 0x78000824
#define STH_MSA_INSN 0x78000825
#define STW_MSA_INSN 0x78000826
#define STD_MSA_INSN 0x78000827
#define COPY_SW_MSA_INSN 0x78b00059
#define COPY_SD_MSA_INSN 0x78b80059
#define INSERT_W_MSA_INSN 0x79300819
#define INSERT_D_MSA_INSN 0x79380819
#endif
/* /*
* Temporary until all toolchains in use include MSA support. * Temporary until all toolchains in use include MSA support.
*/ */
@ -380,8 +370,8 @@
.set push .set push
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
.insn insn_if_mips 0x787e0059 | (\cs << 11)
.word CFC_MSA_INSN | (\cs << 11) insn32_if_mm 0x587e0056 | (\cs << 11)
move \rd, $1 move \rd, $1
.set pop .set pop
.endm .endm
@ -391,7 +381,8 @@
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
move $1, \rs move $1, \rs
.word CTC_MSA_INSN | (\cd << 6) insn_if_mips 0x783e0819 | (\cd << 6)
insn32_if_mm 0x583e0816 | (\cd << 6)
.set pop .set pop
.endm .endm
@ -400,7 +391,8 @@
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
PTR_ADDU $1, \base, \off PTR_ADDU $1, \base, \off
.word LDB_MSA_INSN | (\wd << 6) insn_if_mips 0x78000820 | (\wd << 6)
insn32_if_mm 0x58000807 | (\wd << 6)
.set pop .set pop
.endm .endm
@ -409,7 +401,8 @@
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
PTR_ADDU $1, \base, \off PTR_ADDU $1, \base, \off
.word LDH_MSA_INSN | (\wd << 6) insn_if_mips 0x78000821 | (\wd << 6)
insn32_if_mm 0x58000817 | (\wd << 6)
.set pop .set pop
.endm .endm
@ -418,7 +411,8 @@
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
PTR_ADDU $1, \base, \off PTR_ADDU $1, \base, \off
.word LDW_MSA_INSN | (\wd << 6) insn_if_mips 0x78000822 | (\wd << 6)
insn32_if_mm 0x58000827 | (\wd << 6)
.set pop .set pop
.endm .endm
@ -427,7 +421,8 @@
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
PTR_ADDU $1, \base, \off PTR_ADDU $1, \base, \off
.word LDD_MSA_INSN | (\wd << 6) insn_if_mips 0x78000823 | (\wd << 6)
insn32_if_mm 0x58000837 | (\wd << 6)
.set pop .set pop
.endm .endm
@ -436,7 +431,8 @@
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
PTR_ADDU $1, \base, \off PTR_ADDU $1, \base, \off
.word STB_MSA_INSN | (\wd << 6) insn_if_mips 0x78000824 | (\wd << 6)
insn32_if_mm 0x5800080f | (\wd << 6)
.set pop .set pop
.endm .endm
@ -445,7 +441,8 @@
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
PTR_ADDU $1, \base, \off PTR_ADDU $1, \base, \off
.word STH_MSA_INSN | (\wd << 6) insn_if_mips 0x78000825 | (\wd << 6)
insn32_if_mm 0x5800081f | (\wd << 6)
.set pop .set pop
.endm .endm
@ -454,7 +451,8 @@
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
PTR_ADDU $1, \base, \off PTR_ADDU $1, \base, \off
.word STW_MSA_INSN | (\wd << 6) insn_if_mips 0x78000826 | (\wd << 6)
insn32_if_mm 0x5800082f | (\wd << 6)
.set pop .set pop
.endm .endm
@ -463,7 +461,8 @@
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
PTR_ADDU $1, \base, \off PTR_ADDU $1, \base, \off
.word STD_MSA_INSN | (\wd << 6) insn_if_mips 0x78000827 | (\wd << 6)
insn32_if_mm 0x5800083f | (\wd << 6)
.set pop .set pop
.endm .endm
@ -471,8 +470,8 @@
.set push .set push
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
.insn insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
.word COPY_SW_MSA_INSN | (\n << 16) | (\ws << 11) insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
.set pop .set pop
.endm .endm
@ -480,8 +479,8 @@
.set push .set push
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
.insn insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
.word COPY_SD_MSA_INSN | (\n << 16) | (\ws << 11) insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
.set pop .set pop
.endm .endm
@ -489,7 +488,8 @@
.set push .set push
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
.word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6) insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
.set pop .set pop
.endm .endm
@ -497,7 +497,8 @@
.set push .set push
.set noat .set noat
SET_HARDFLOAT SET_HARDFLOAT
.word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6) insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
.set pop .set pop
.endm .endm
#endif #endif

8
arch/mips/include/asm/hazards.h
View File

@ -58,8 +58,8 @@
* address of a label as argument to inline assembler. Gas otoh has the * address of a label as argument to inline assembler. Gas otoh has the
* annoying difference between la and dla which are only usable for 32-bit * annoying difference between la and dla which are only usable for 32-bit
* rsp. 64-bit code, so can't be used without conditional compilation. * rsp. 64-bit code, so can't be used without conditional compilation.
* The alterantive is switching the assembler to 64-bit code which happens * The alternative is switching the assembler to 64-bit code which happens
* to work right even for 32-bit code ... * to work right even for 32-bit code...
*/ */
#define instruction_hazard() \ #define instruction_hazard() \
do { \ do { \
@ -133,8 +133,8 @@ do { \
* address of a label as argument to inline assembler. Gas otoh has the * address of a label as argument to inline assembler. Gas otoh has the
* annoying difference between la and dla which are only usable for 32-bit * annoying difference between la and dla which are only usable for 32-bit
* rsp. 64-bit code, so can't be used without conditional compilation. * rsp. 64-bit code, so can't be used without conditional compilation.
* The alterantive is switching the assembler to 64-bit code which happens * The alternative is switching the assembler to 64-bit code which happens
* to work right even for 32-bit code ... * to work right even for 32-bit code...
*/ */
#define __instruction_hazard() \ #define __instruction_hazard() \
do { \ do { \

2
arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
View File

@ -100,7 +100,7 @@ typedef volatile struct au1xxx_ddma_desc {
u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
/* /*
* First 32 bytes are HW specific!!! * First 32 bytes are HW specific!!!
* Lets have some SW data following -- make sure it's 32 bytes. * Let's have some SW data following -- make sure it's 32 bytes.
*/ */
u32 sw_status; u32 sw_status;
u32 sw_context; u32 sw_context;

2
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
View File

@ -140,7 +140,7 @@ static inline int au1300_gpio_getinitlvl(unsigned int gpio)
* Cases 1 and 3 are intended for boards which want to provide their own * Cases 1 and 3 are intended for boards which want to provide their own
* GPIO namespace and -operations (i.e. for example you have 8 GPIOs * GPIO namespace and -operations (i.e. for example you have 8 GPIOs
* which are in part provided by spare Au1300 GPIO pins and in part by * which are in part provided by spare Au1300 GPIO pins and in part by
* an external FPGA but you still want them to be accssible in linux * an external FPGA but you still want them to be accessible in linux
* as gpio0-7. The board can of course use the alchemy_gpioX_* functions * as gpio0-7. The board can of course use the alchemy_gpioX_* functions
* as required). * as required).
*/ */

2
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
View File

@ -22,7 +22,7 @@ struct bcm63xx_enet_platform_data {
int has_phy_interrupt; int has_phy_interrupt;
int phy_interrupt; int phy_interrupt;
/* if has_phy, use autonegociated pause parameters or force /* if has_phy, use autonegotiated pause parameters or force
* them */ * them */
int pause_auto; int pause_auto;
int pause_rx; int pause_rx;

2
arch/mips/include/asm/mach-ip27/dma-coherence.h
View File

@ -64,7 +64,7 @@ static inline void plat_post_dma_flush(struct device *dev)
static inline int plat_device_is_coherent(struct device *dev) static inline int plat_device_is_coherent(struct device *dev)
{ {
return 1; /* IP27 non-cohernet mode is unsupported */ return 1; /* IP27 non-coherent mode is unsupported */
} }
#endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */ #endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */

2
arch/mips/include/asm/mach-ip32/dma-coherence.h
View File

@ -86,7 +86,7 @@ static inline void plat_post_dma_flush(struct device *dev)
static inline int plat_device_is_coherent(struct device *dev) static inline int plat_device_is_coherent(struct device *dev)
{ {
return 0; /* IP32 is non-cohernet */ return 0; /* IP32 is non-coherent */
} }
#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */ #endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */

2
arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
View File

@ -22,7 +22,7 @@
/* /*
* during early_printk no ioremap possible at this early stage * during early_printk no ioremap possible at this early stage
* lets use KSEG1 instead * let's use KSEG1 instead
*/ */
#define LTQ_ASC0_BASE_ADDR 0x1E100C00 #define LTQ_ASC0_BASE_ADDR 0x1E100C00
#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) #define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)

2
arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
View File

@ -75,7 +75,7 @@ extern __iomem void *ltq_cgu_membase;
/* /*
* during early_printk no ioremap is possible * during early_printk no ioremap is possible
* lets use KSEG1 instead * let's use KSEG1 instead
*/ */
#define LTQ_ASC1_BASE_ADDR 0x1E100C00 #define LTQ_ASC1_BASE_ADDR 0x1E100C00
#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) #define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)

2
arch/mips/include/asm/mach-loongson64/loongson_hwmon.h
View File

@ -24,7 +24,7 @@ struct temp_range {
u8 level; u8 level;
}; };
#define CONSTANT_SPEED_POLICY 0 /* at constent speed */ #define CONSTANT_SPEED_POLICY 0 /* at constant speed */
#define STEP_SPEED_POLICY 1 /* use up/down arrays to describe policy */ #define STEP_SPEED_POLICY 1 /* use up/down arrays to describe policy */
#define KERNEL_HELPER_POLICY 2 /* kernel as a helper to fan control */ #define KERNEL_HELPER_POLICY 2 /* kernel as a helper to fan control */

6
arch/mips/include/asm/mach-malta/kernel-entry-init.h
View File

@ -56,7 +56,7 @@
(0 << MIPS_SEGCFG_PA_SHIFT) | \ (0 << MIPS_SEGCFG_PA_SHIFT) | \
(1 << MIPS_SEGCFG_EU_SHIFT)) << 16) (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
or t0, t2 or t0, t2
mtc0 t0, $5, 2 mtc0 t0, CP0_SEGCTL0
/* SegCtl1 */ /* SegCtl1 */
li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
@ -67,7 +67,7 @@
(0 << MIPS_SEGCFG_PA_SHIFT) | \ (0 << MIPS_SEGCFG_PA_SHIFT) | \
(1 << MIPS_SEGCFG_EU_SHIFT)) << 16) (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
ins t0, t1, 16, 3 ins t0, t1, 16, 3
mtc0 t0, $5, 3 mtc0 t0, CP0_SEGCTL1
/* SegCtl2 */ /* SegCtl2 */
li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
@ -77,7 +77,7 @@
(4 << MIPS_SEGCFG_PA_SHIFT) | \ (4 << MIPS_SEGCFG_PA_SHIFT) | \
(1 << MIPS_SEGCFG_EU_SHIFT)) << 16) (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
or t0, t2 or t0, t2
mtc0 t0, $5, 4 mtc0 t0, CP0_SEGCTL2
jal mips_ihb jal mips_ihb
mfc0 t0, $16, 5 mfc0 t0, $16, 5

2
arch/mips/include/asm/mips_mt.h
View File

@ -1,5 +1,5 @@
/* /*
* Definitions and decalrations for MIPS MT support that are common between * Definitions and declarations for MIPS MT support that are common between
* the VSMP, and AP/SP kernel models. * the VSMP, and AP/SP kernel models.
*/ */
#ifndef __ASM_MIPS_MT_H #ifndef __ASM_MIPS_MT_H

194
arch/mips/include/asm/mipsregs.h
View File

@ -48,6 +48,9 @@
#define CP0_CONF $3 #define CP0_CONF $3
#define CP0_CONTEXT $4 #define CP0_CONTEXT $4
#define CP0_PAGEMASK $5 #define CP0_PAGEMASK $5
#define CP0_SEGCTL0 $5, 2
#define CP0_SEGCTL1 $5, 3
#define CP0_SEGCTL2 $5, 4
#define CP0_WIRED $6 #define CP0_WIRED $6
#define CP0_INFO $7 #define CP0_INFO $7
#define CP0_HWRENA $7, 0 #define CP0_HWRENA $7, 0
@ -726,6 +729,8 @@
#define MIPS_PWFIELD_PTEI_SHIFT 0 #define MIPS_PWFIELD_PTEI_SHIFT 0
#define MIPS_PWFIELD_PTEI_MASK 0x0000003f #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
#define MIPS_PWSIZE_PS_SHIFT 30
#define MIPS_PWSIZE_PS_MASK 0x40000000
#define MIPS_PWSIZE_GDW_SHIFT 24 #define MIPS_PWSIZE_GDW_SHIFT 24
#define MIPS_PWSIZE_GDW_MASK 0x3f000000 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
#define MIPS_PWSIZE_UDW_SHIFT 18 #define MIPS_PWSIZE_UDW_SHIFT 18
@ -739,6 +744,12 @@
#define MIPS_PWCTL_PWEN_SHIFT 31 #define MIPS_PWCTL_PWEN_SHIFT 31
#define MIPS_PWCTL_PWEN_MASK 0x80000000 #define MIPS_PWCTL_PWEN_MASK 0x80000000
#define MIPS_PWCTL_XK_SHIFT 28
#define MIPS_PWCTL_XK_MASK 0x10000000
#define MIPS_PWCTL_XS_SHIFT 27
#define MIPS_PWCTL_XS_MASK 0x08000000
#define MIPS_PWCTL_XU_SHIFT 26
#define MIPS_PWCTL_XU_MASK 0x04000000
#define MIPS_PWCTL_DPH_SHIFT 7 #define MIPS_PWCTL_DPH_SHIFT 7
#define MIPS_PWCTL_DPH_MASK 0x00000080 #define MIPS_PWCTL_DPH_MASK 0x00000080
#define MIPS_PWCTL_HUGEPG_SHIFT 6 #define MIPS_PWCTL_HUGEPG_SHIFT 6
@ -1045,6 +1056,33 @@ static inline int mm_insn_16bit(u16 insn)
return (opcode >= 1 && opcode <= 3) ? 1 : 0; return (opcode >= 1 && opcode <= 3) ? 1 : 0;
} }
/*
* Helper macros for generating raw instruction encodings in inline asm.
*/
#ifdef CONFIG_CPU_MICROMIPS
#define _ASM_INSN16_IF_MM(_enc) \
".insn\n\t" \
".hword (" #_enc ")\n\t"
#define _ASM_INSN32_IF_MM(_enc) \
".insn\n\t" \
".hword ((" #_enc ") >> 16)\n\t" \
".hword ((" #_enc ") & 0xffff)\n\t"
#else
#define _ASM_INSN_IF_MIPS(_enc) \
".insn\n\t" \
".word (" #_enc ")\n\t"
#endif
#ifndef _ASM_INSN16_IF_MM
#define _ASM_INSN16_IF_MM(_enc)
#endif
#ifndef _ASM_INSN32_IF_MM
#define _ASM_INSN32_IF_MM(_enc)
#endif
#ifndef _ASM_INSN_IF_MIPS
#define _ASM_INSN_IF_MIPS(_enc)
#endif
/* /*
* TLB Invalidate Flush * TLB Invalidate Flush
*/ */
@ -1053,7 +1091,9 @@ static inline void tlbinvf(void)
__asm__ __volatile__( __asm__ __volatile__(
".set push\n\t" ".set push\n\t"
".set noreorder\n\t" ".set noreorder\n\t"
".word 0x42000004\n\t" /* tlbinvf */ "# tlbinvf\n\t"
_ASM_INSN_IF_MIPS(0x42000004)
_ASM_INSN32_IF_MM(0x0000537c)
".set pop"); ".set pop");
} }
@ -1274,9 +1314,9 @@ do { \
" .set push \n" \ " .set push \n" \
" .set noat \n" \ " .set noat \n" \
" .set mips32r2 \n" \ " .set mips32r2 \n" \
" .insn \n" \
" # mfhc0 $1, %1 \n" \ " # mfhc0 $1, %1 \n" \
" .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \ _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11)) \
_ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16)) \
" move %0, $1 \n" \ " move %0, $1 \n" \
" .set pop \n" \ " .set pop \n" \
: "=r" (__res) \ : "=r" (__res) \
@ -1292,8 +1332,8 @@ do { \
" .set mips32r2 \n" \ " .set mips32r2 \n" \
" move $1, %0 \n" \ " move $1, %0 \n" \
" # mthc0 $1, %1 \n" \ " # mthc0 $1, %1 \n" \
" .insn \n" \ _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11)) \
" .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \ _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16)) \
" .set pop \n" \ " .set pop \n" \
: \ : \
: "r" (value), "i" (register)); \ : "r" (value), "i" (register)); \
@ -1743,7 +1783,8 @@ do { \
".set\tpush\n\t" \ ".set\tpush\n\t" \
".set\tnoat\n\t" \ ".set\tnoat\n\t" \
"# mfgc0\t$1, $%1, %2\n\t" \ "# mfgc0\t$1, $%1, %2\n\t" \
".word\t(0x40610000 | %1 << 11 | %2)\n\t" \ _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2) \
_ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11) \
"move\t%0, $1\n\t" \ "move\t%0, $1\n\t" \
".set\tpop" \ ".set\tpop" \
: "=r" (__res) \ : "=r" (__res) \
@ -1757,7 +1798,8 @@ do { \
".set\tpush\n\t" \ ".set\tpush\n\t" \
".set\tnoat\n\t" \ ".set\tnoat\n\t" \
"# dmfgc0\t$1, $%1, %2\n\t" \ "# dmfgc0\t$1, $%1, %2\n\t" \
".word\t(0x40610100 | %1 << 11 | %2)\n\t" \ _ASM_INSN_IF_MIPS(0x40610100 | %1 << 11 | %2) \
_ASM_INSN32_IF_MM(0x582004fc | %1 << 16 | %2 << 11) \
"move\t%0, $1\n\t" \ "move\t%0, $1\n\t" \
".set\tpop" \ ".set\tpop" \
: "=r" (__res) \ : "=r" (__res) \
@ -1770,9 +1812,10 @@ do { \
__asm__ __volatile__( \ __asm__ __volatile__( \
".set\tpush\n\t" \ ".set\tpush\n\t" \
".set\tnoat\n\t" \ ".set\tnoat\n\t" \
"move\t$1, %0\n\t" \ "move\t$1, %z0\n\t" \
"# mtgc0\t$1, $%1, %2\n\t" \ "# mtgc0\t$1, $%1, %2\n\t" \
".word\t(0x40610200 | %1 << 11 | %2)\n\t" \ _ASM_INSN_IF_MIPS(0x40610200 | %1 << 11 | %2) \
_ASM_INSN32_IF_MM(0x002006fc | %1 << 16 | %2 << 11) \
".set\tpop" \ ".set\tpop" \
: : "Jr" ((unsigned int)(value)), \ : : "Jr" ((unsigned int)(value)), \
"i" (register), "i" (sel)); \ "i" (register), "i" (sel)); \
@ -1783,9 +1826,10 @@ do { \
__asm__ __volatile__( \ __asm__ __volatile__( \
".set\tpush\n\t" \ ".set\tpush\n\t" \
".set\tnoat\n\t" \ ".set\tnoat\n\t" \
"move\t$1, %0\n\t" \ "move\t$1, %z0\n\t" \
"# dmtgc0\t$1, $%1, %2\n\t" \ "# dmtgc0\t$1, $%1, %2\n\t" \
".word\t(0x40610300 | %1 << 11 | %2)\n\t" \ _ASM_INSN_IF_MIPS(0x40610300 | %1 << 11 | %2) \
_ASM_INSN32_IF_MM(0x582006fc | %1 << 16 | %2 << 11) \
".set\tpop" \ ".set\tpop" \
: : "Jr" (value), \ : : "Jr" (value), \
"i" (register), "i" (sel)); \ "i" (register), "i" (sel)); \
@ -2246,7 +2290,6 @@ do { \
#else #else
#ifdef CONFIG_CPU_MICROMIPS
#define rddsp(mask) \ #define rddsp(mask) \
({ \ ({ \
unsigned int __res; \ unsigned int __res; \
@ -2255,8 +2298,8 @@ do { \
" .set push \n" \ " .set push \n" \
" .set noat \n" \ " .set noat \n" \
" # rddsp $1, %x1 \n" \ " # rddsp $1, %x1 \n" \
" .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
" .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
" move %0, $1 \n" \ " move %0, $1 \n" \
" .set pop \n" \ " .set pop \n" \
: "=r" (__res) \ : "=r" (__res) \
@ -2271,98 +2314,13 @@ do { \
" .set noat \n" \ " .set noat \n" \
" move $1, %0 \n" \ " move $1, %0 \n" \
" # wrdsp $1, %x1 \n" \ " # wrdsp $1, %x1 \n" \
" .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
" .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
" .set pop \n" \ " .set pop \n" \
: \ : \
: "r" (val), "i" (mask)); \ : "r" (val), "i" (mask)); \
} while (0) } while (0)
#define _umips_dsp_mfxxx(ins) \
({ \
unsigned long __treg; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" .hword 0x0001 \n" \
" .hword %x1 \n" \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__treg) \
: "i" (ins)); \
__treg; \
})
#define _umips_dsp_mtxxx(val, ins) \
do { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
" .hword 0x0001 \n" \
" .hword %x1 \n" \
" .set pop \n" \
: \
: "r" (val), "i" (ins)); \
} while (0)
#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
#define mflo0() _umips_dsp_mflo(0)
#define mflo1() _umips_dsp_mflo(1)
#define mflo2() _umips_dsp_mflo(2)
#define mflo3() _umips_dsp_mflo(3)
#define mfhi0() _umips_dsp_mfhi(0)
#define mfhi1() _umips_dsp_mfhi(1)
#define mfhi2() _umips_dsp_mfhi(2)
#define mfhi3() _umips_dsp_mfhi(3)
#define mtlo0(x) _umips_dsp_mtlo(x, 0)
#define mtlo1(x) _umips_dsp_mtlo(x, 1)
#define mtlo2(x) _umips_dsp_mtlo(x, 2)
#define mtlo3(x) _umips_dsp_mtlo(x, 3)
#define mthi0(x) _umips_dsp_mthi(x, 0)
#define mthi1(x) _umips_dsp_mthi(x, 1)
#define mthi2(x) _umips_dsp_mthi(x, 2)
#define mthi3(x) _umips_dsp_mthi(x, 3)
#else /* !CONFIG_CPU_MICROMIPS */
#define rddsp(mask) \
({ \
unsigned int __res; \
\
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" # rddsp $1, %x1 \n" \
" .word 0x7c000cb8 | (%x1 << 16) \n" \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__res) \
: "i" (mask)); \
__res; \
})
#define wrdsp(val, mask) \
do { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" move $1, %0 \n" \
" # wrdsp $1, %x1 \n" \
" .word 0x7c2004f8 | (%x1 << 11) \n" \
" .set pop \n" \
: \
: "r" (val), "i" (mask)); \
} while (0)
#define _dsp_mfxxx(ins) \ #define _dsp_mfxxx(ins) \
({ \ ({ \
unsigned long __treg; \ unsigned long __treg; \
@ -2370,7 +2328,8 @@ do { \
__asm__ __volatile__( \ __asm__ __volatile__( \
" .set push \n" \ " .set push \n" \
" .set noat \n" \ " .set noat \n" \
" .word (0x00000810 | %1) \n" \ _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
_ASM_INSN32_IF_MM(0x0001007c | %x1) \
" move %0, $1 \n" \ " move %0, $1 \n" \
" .set pop \n" \ " .set pop \n" \
: "=r" (__treg) \ : "=r" (__treg) \
@ -2384,18 +2343,31 @@ do { \
" .set push \n" \ " .set push \n" \
" .set noat \n" \ " .set noat \n" \
" move $1, %0 \n" \ " move $1, %0 \n" \
" .word (0x00200011 | %1) \n" \ _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
_ASM_INSN32_IF_MM(0x0001207c | %x1) \
" .set pop \n" \ " .set pop \n" \
: \ : \
: "r" (val), "i" (ins)); \ : "r" (val), "i" (ins)); \
} while (0) } while (0)
#ifdef CONFIG_CPU_MICROMIPS
#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
#else /* !CONFIG_CPU_MICROMIPS */
#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
#endif /* CONFIG_CPU_MICROMIPS */
#define mflo0() _dsp_mflo(0) #define mflo0() _dsp_mflo(0)
#define mflo1() _dsp_mflo(1) #define mflo1() _dsp_mflo(1)
#define mflo2() _dsp_mflo(2) #define mflo2() _dsp_mflo(2)
@ -2416,7 +2388,6 @@ do { \
#define mthi2(x) _dsp_mthi(x, 2) #define mthi2(x) _dsp_mthi(x, 2)
#define mthi3(x) _dsp_mthi(x, 3) #define mthi3(x) _dsp_mthi(x, 3)
#endif /* CONFIG_CPU_MICROMIPS */
#endif #endif
/* /*
@ -2556,28 +2527,32 @@ static inline void guest_tlb_probe(void)
{ {
__asm__ __volatile__( __asm__ __volatile__(
"# tlbgp\n\t" "# tlbgp\n\t"
".word 0x42000010"); _ASM_INSN_IF_MIPS(0x42000010)
_ASM_INSN32_IF_MM(0x0000017c));
} }
static inline void guest_tlb_read(void) static inline void guest_tlb_read(void)
{ {
__asm__ __volatile__( __asm__ __volatile__(
"# tlbgr\n\t" "# tlbgr\n\t"
".word 0x42000009"); _ASM_INSN_IF_MIPS(0x42000009)
_ASM_INSN32_IF_MM(0x0000117c));
} }
static inline void guest_tlb_write_indexed(void) static inline void guest_tlb_write_indexed(void)
{ {
__asm__ __volatile__( __asm__ __volatile__(
"# tlbgwi\n\t" "# tlbgwi\n\t"
".word 0x4200000a"); _ASM_INSN_IF_MIPS(0x4200000a)
_ASM_INSN32_IF_MM(0x0000217c));
} }
static inline void guest_tlb_write_random(void) static inline void guest_tlb_write_random(void)
{ {
__asm__ __volatile__( __asm__ __volatile__(
"# tlbgwr\n\t" "# tlbgwr\n\t"
".word 0x4200000e"); _ASM_INSN_IF_MIPS(0x4200000e)
_ASM_INSN32_IF_MM(0x0000317c));
} }
/* /*
@ -2587,7 +2562,8 @@ static inline void guest_tlbinvf(void)
{ {
__asm__ __volatile__( __asm__ __volatile__(
"# tlbginvf\n\t" "# tlbginvf\n\t"
".word 0x4200000c"); _ASM_INSN_IF_MIPS(0x4200000c)
_ASM_INSN32_IF_MM(0x0000517c));
} }
#endif /* !TOOLCHAIN_SUPPORTS_VIRT */ #endif /* !TOOLCHAIN_SUPPORTS_VIRT */

21
arch/mips/include/asm/msa.h
View File

@ -192,13 +192,6 @@ static inline void write_msa_##name(unsigned int val) \
* allow compilation with toolchains that do not support MSA. Once all * allow compilation with toolchains that do not support MSA. Once all
* toolchains in use support MSA these can be removed. * toolchains in use support MSA these can be removed.
*/ */
#ifdef CONFIG_CPU_MICROMIPS
#define CFC_MSA_INSN 0x587e0056
#define CTC_MSA_INSN 0x583e0816
#else
#define CFC_MSA_INSN 0x787e0059
#define CTC_MSA_INSN 0x783e0819
#endif
#define __BUILD_MSA_CTL_REG(name, cs) \ #define __BUILD_MSA_CTL_REG(name, cs) \
static inline unsigned int read_msa_##name(void) \ static inline unsigned int read_msa_##name(void) \
@ -207,11 +200,12 @@ static inline unsigned int read_msa_##name(void) \
__asm__ __volatile__( \ __asm__ __volatile__( \
" .set push\n" \ " .set push\n" \
" .set noat\n" \ " .set noat\n" \
" .insn\n" \ " # cfcmsa $1, $%1\n" \
" .word %1 | (" #cs " << 11)\n" \ _ASM_INSN_IF_MIPS(0x787e0059 | %1 << 11) \
_ASM_INSN32_IF_MM(0x587e0056 | %1 << 11) \
" move %0, $1\n" \ " move %0, $1\n" \
" .set pop\n" \ " .set pop\n" \
: "=r"(reg) : "i"(CFC_MSA_INSN)); \ : "=r"(reg) : "i"(cs)); \
return reg; \ return reg; \
} \ } \
\ \
@ -221,10 +215,11 @@ static inline void write_msa_##name(unsigned int val) \
" .set push\n" \ " .set push\n" \
" .set noat\n" \ " .set noat\n" \
" move $1, %0\n" \ " move $1, %0\n" \
" .insn\n" \ " # ctcmsa $%1, $1\n" \
" .word %1 | (" #cs " << 6)\n" \ _ASM_INSN_IF_MIPS(0x783e0819 | %1 << 6) \
_ASM_INSN32_IF_MM(0x583e0816 | %1 << 6) \
" .set pop\n" \ " .set pop\n" \
: : "r"(val), "i"(CTC_MSA_INSN)); \ : : "r"(val), "i"(cs)); \
} }
#endif /* !TOOLCHAIN_SUPPORTS_MSA */ #endif /* !TOOLCHAIN_SUPPORTS_MSA */

2
arch/mips/include/asm/octeon/cvmx-cmd-queue.h
View File

@ -146,7 +146,7 @@ typedef struct {
* This structure contains the global state of all command queues. * This structure contains the global state of all command queues.
* It is stored in a bootmem named block and shared by all * It is stored in a bootmem named block and shared by all
* applications running on Octeon. Tickets are stored in a differnet * applications running on Octeon. Tickets are stored in a differnet
* cahce line that queue information to reduce the contention on the * cache line that queue information to reduce the contention on the
* ll/sc used to get a ticket. If this is not the case, the update * ll/sc used to get a ticket. If this is not the case, the update
* of queue state causes the ll/sc to fail quite often. * of queue state causes the ll/sc to fail quite often.
*/ */

2
arch/mips/include/asm/octeon/cvmx-helper-board.h
View File

@ -94,7 +94,7 @@ extern int cvmx_helper_board_get_mii_address(int ipd_port);
* @phy_addr: The address of the PHY to program * @phy_addr: The address of the PHY to program
* @link_flags: * @link_flags:
* Flags to control autonegotiation. Bit 0 is autonegotiation * Flags to control autonegotiation. Bit 0 is autonegotiation
* enable/disable to maintain backware compatibility. * enable/disable to maintain backward compatibility.
* @link_info: Link speed to program. If the speed is zero and autonegotiation * @link_info: Link speed to program. If the speed is zero and autonegotiation
* is enabled, all possible negotiation speeds are advertised. * is enabled, all possible negotiation speeds are advertised.
* *

2
arch/mips/include/asm/octeon/cvmx-ipd.h
View File

@ -39,7 +39,7 @@
enum cvmx_ipd_mode { enum cvmx_ipd_mode {
CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */
CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */ CVMX_IPD_OPC_MODE_STF = 1LL, /* All blocks into L2 */
CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */ CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */
CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */ CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */
}; };

2
arch/mips/include/asm/octeon/cvmx-pow.h
View File

@ -2051,7 +2051,7 @@ static inline void cvmx_pow_tag_sw_desched(uint32_t tag,
} }
/** /**
* Descchedules the current work queue entry. * Deschedules the current work queue entry.
* *
* @no_sched: no schedule flag value to be set on the work queue * @no_sched: no schedule flag value to be set on the work queue
* entry. If this is set the entry will not be * entry. If this is set the entry will not be

2
arch/mips/include/asm/sgi/hpc3.h
View File

@ -39,7 +39,7 @@ struct hpc3_pbus_dmacregs {
volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */ volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
u32 _unused0[0x1000/4 - 2]; /* padding */ u32 _unused0[0x1000/4 - 2]; /* padding */
volatile u32 pbdma_ctrl; /* pbus dma channel control register has volatile u32 pbdma_ctrl; /* pbus dma channel control register has
* copletely different meaning for read * completely different meaning for read
* compared with write */ * compared with write */
/* read */ /* read */
#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */ #define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */

4
arch/mips/kernel/branch.c
View File

@ -481,7 +481,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
/* /*
* OK we are here either because we hit a NAL * OK we are here either because we hit a NAL
* instruction or because we are emulating an * instruction or because we are emulating an
* old bltzal{,l} one. Lets figure out what the * old bltzal{,l} one. Let's figure out what the
* case really is. * case really is.
*/ */
if (!insn.i_format.rs) { if (!insn.i_format.rs) {
@ -515,7 +515,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
/* /*
* OK we are here either because we hit a BAL * OK we are here either because we hit a BAL
* instruction or because we are emulating an * instruction or because we are emulating an
* old bgezal{,l} one. Lets figure out what the * old bgezal{,l} one. Let's figure out what the
* case really is. * case really is.
*/ */
if (!insn.i_format.rs) { if (!insn.i_format.rs) {

15
arch/mips/kernel/cps-vec.S
View File

@ -441,6 +441,21 @@ LEAF(mips_cps_boot_vpes)
mfc0 t0, CP0_CONFIG mfc0 t0, CP0_CONFIG
mttc0 t0, CP0_CONFIG mttc0 t0, CP0_CONFIG
/*
* Copy the EVA config from this VPE if the CPU supports it.
* CONFIG3 must exist to be running MT startup - just read it.
*/
mfc0 t0, CP0_CONFIG, 3
and t0, t0, MIPS_CONF3_SC
beqz t0, 3f
nop
mfc0 t0, CP0_SEGCTL0
mttc0 t0, CP0_SEGCTL0
mfc0 t0, CP0_SEGCTL1
mttc0 t0, CP0_SEGCTL1
mfc0 t0, CP0_SEGCTL2
mttc0 t0, CP0_SEGCTL2
3:
/* Ensure no software interrupts are pending */ /* Ensure no software interrupts are pending */
mttc0 zero, CP0_CAUSE mttc0 zero, CP0_CAUSE
mttc0 zero, CP0_STATUS mttc0 zero, CP0_STATUS

4
arch/mips/kernel/cpu-probe.c
View File

@ -833,10 +833,8 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
c->options |= MIPS_CPU_MAAR; c->options |= MIPS_CPU_MAAR;
if (config5 & MIPS_CONF5_LLB) if (config5 & MIPS_CONF5_LLB)
c->options |= MIPS_CPU_RW_LLB; c->options |= MIPS_CPU_RW_LLB;
#ifdef CONFIG_XPA
if (config5 & MIPS_CONF5_MVH) if (config5 & MIPS_CONF5_MVH)
c->options |= MIPS_CPU_XPA; c->options |= MIPS_CPU_MVH;
#endif
if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
c->options |= MIPS_CPU_VP; c->options |= MIPS_CPU_VP;

2
arch/mips/kernel/elf.c
View File

@ -88,7 +88,7 @@ int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf,
elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32; elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags; flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags;
/* Lets see if this is an O32 ELF */ /* Let's see if this is an O32 ELF */
if (elf32) { if (elf32) {
if (flags & EF_MIPS_FP64) { if (flags & EF_MIPS_FP64) {
/* /*

3
arch/mips/kernel/irq.c
View File

@ -54,6 +54,9 @@ void __init init_IRQ(void)
for (i = 0; i < NR_IRQS; i++) for (i = 0; i < NR_IRQS; i++)
irq_set_noprobe(i); irq_set_noprobe(i);
if (cpu_has_veic)
clear_c0_status(ST0_IM);
arch_init_irq(); arch_init_irq();
} }

2
arch/mips/kernel/mips-r2-to-r6-emul.c
View File

@ -2202,7 +2202,7 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
} }
/* /*
* Lets not return to userland just yet. It's constly and * Let's not return to userland just yet. It's costly and
* it's likely we have more R2 instructions to emulate * it's likely we have more R2 instructions to emulate
*/ */
if (!err && (pass++ < MIPS_R2_EMUL_TOTAL_PASS)) { if (!err && (pass++ < MIPS_R2_EMUL_TOTAL_PASS)) {

2
arch/mips/kernel/process.c
View File

@ -345,7 +345,7 @@ static int get_frame_info(struct mips_frame_info *info)
return 0; return 0;
if (info->pc_offset < 0) /* leaf */ if (info->pc_offset < 0) /* leaf */
return 1; return 1;
/* prologue seems boggus... */ /* prologue seems bogus... */
err: err:
return -1; return -1;
} }

8
arch/mips/kernel/signal.c
View File

@ -770,15 +770,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
sigset_t *oldset = sigmask_to_save(); sigset_t *oldset = sigmask_to_save();
int ret; int ret;
struct mips_abi *abi = current->thread.abi; struct mips_abi *abi = current->thread.abi;
#ifdef CONFIG_CPU_MICROMIPS
void *vdso;
unsigned long tmp = (unsigned long)current->mm->context.vdso;
set_isa16_mode(tmp);
vdso = (void *)tmp;
#else
void *vdso = current->mm->context.vdso; void *vdso = current->mm->context.vdso;
#endif
if (regs->regs[0]) { if (regs->regs[0]) {
switch(regs->regs[2]) { switch(regs->regs[2]) {

8
arch/mips/kernel/smp-cps.c
View File

@ -359,8 +359,12 @@ static void cps_init_secondary(void)
BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
} }
change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | if (cpu_has_veic)
STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7); clear_c0_status(ST0_IM);
else
change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
STATUSF_IP4 | STATUSF_IP5 |
STATUSF_IP6 | STATUSF_IP7);
} }
static void cps_smp_finish(void) static void cps_smp_finish(void)

4
arch/mips/lasat/picvue_proc.c
View File

@ -43,7 +43,7 @@ static int pvc_line_proc_show(struct seq_file *m, void *v)
{ {
int lineno = *(int *)m->private; int lineno = *(int *)m->private;
if (lineno < 0 || lineno > PVC_NLINES) { if (lineno < 0 || lineno >= PVC_NLINES) {
printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno); printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno);
return 0; return 0;
} }
@ -67,7 +67,7 @@ static ssize_t pvc_line_proc_write(struct file *file, const char __user *buf,
char kbuf[PVC_LINELEN]; char kbuf[PVC_LINELEN];
size_t len; size_t len;
BUG_ON(lineno < 0 || lineno > PVC_NLINES); BUG_ON(lineno < 0 || lineno >= PVC_NLINES);
len = min(count, sizeof(kbuf) - 1); len = min(count, sizeof(kbuf) - 1);
if (copy_from_user(kbuf, buf, len)) if (copy_from_user(kbuf, buf, len))

2
arch/mips/lib/ashldi3.c
View File

@ -2,7 +2,7 @@
#include "libgcc.h" #include "libgcc.h"
long long __ashldi3(long long u, word_type b) long long notrace __ashldi3(long long u, word_type b)
{ {
DWunion uu, w; DWunion uu, w;
word_type bm; word_type bm;

2
arch/mips/lib/ashrdi3.c
View File

@ -2,7 +2,7 @@
#include "libgcc.h" #include "libgcc.h"
long long __ashrdi3(long long u, word_type b) long long notrace __ashrdi3(long long u, word_type b)
{ {
DWunion uu, w; DWunion uu, w;
word_type bm; word_type bm;

2
arch/mips/lib/bswapdi.c
View File

@ -1,6 +1,6 @@
#include <linux/module.h> #include <linux/module.h>
unsigned long long __bswapdi2(unsigned long long u) unsigned long long notrace __bswapdi2(unsigned long long u)
{ {
return (((u) & 0xff00000000000000ull) >> 56) | return (((u) & 0xff00000000000000ull) >> 56) |
(((u) & 0x00ff000000000000ull) >> 40) | (((u) & 0x00ff000000000000ull) >> 40) |

2
arch/mips/lib/bswapsi.c
View File

@ -1,6 +1,6 @@
#include <linux/module.h> #include <linux/module.h>
unsigned int __bswapsi2(unsigned int u) unsigned int notrace __bswapsi2(unsigned int u)
{ {
return (((u) & 0xff000000) >> 24) | return (((u) & 0xff000000) >> 24) |
(((u) & 0x00ff0000) >> 8) | (((u) & 0x00ff0000) >> 8) |

2
arch/mips/lib/cmpdi2.c
View File

@ -2,7 +2,7 @@
#include "libgcc.h" #include "libgcc.h"
word_type __cmpdi2(long long a, long long b) word_type notrace __cmpdi2(long long a, long long b)
{ {
const DWunion au = { const DWunion au = {
.ll = a .ll = a

2
arch/mips/lib/lshrdi3.c
View File

@ -2,7 +2,7 @@
#include "libgcc.h" #include "libgcc.h"
long long __lshrdi3(long long u, word_type b) long long notrace __lshrdi3(long long u, word_type b)
{ {
DWunion uu, w; DWunion uu, w;
word_type bm; word_type bm;

2
arch/mips/lib/memcpy.S
View File

@ -256,7 +256,7 @@
/* /*
* Macro to build the __copy_user common code * Macro to build the __copy_user common code
* Arguements: * Arguments:
* mode : LEGACY_MODE or EVA_MODE * mode : LEGACY_MODE or EVA_MODE
* from : Source operand. USEROP or KERNELOP * from : Source operand. USEROP or KERNELOP
* to : Destination operand. USEROP or KERNELOP * to : Destination operand. USEROP or KERNELOP

2
arch/mips/lib/ucmpdi2.c
View File

@ -2,7 +2,7 @@
#include "libgcc.h" #include "libgcc.h"
word_type __ucmpdi2(unsigned long long a, unsigned long long b) word_type notrace __ucmpdi2(unsigned long long a, unsigned long long b)
{ {
const DWunion au = {.ll = a}; const DWunion au = {.ll = a};
const DWunion bu = {.ll = b}; const DWunion bu = {.ll = b};

2
arch/mips/loongson64/loongson-3/hpet.c
View File

@ -212,7 +212,7 @@ static void hpet_setup(void)
/* set hpet base address */ /* set hpet base address */
smbus_write(SMBUS_PCI_REGB4, HPET_ADDR); smbus_write(SMBUS_PCI_REGB4, HPET_ADDR);
/* enable decodeing of access to HPET MMIO*/ /* enable decoding of access to HPET MMIO*/
smbus_enable(SMBUS_PCI_REG40, (1 << 28)); smbus_enable(SMBUS_PCI_REG40, (1 << 28));
/* HPET irq enable */ /* HPET irq enable */

4
arch/mips/math-emu/dsemul.c
View File

@ -8,7 +8,7 @@
#include "ieee754.h" #include "ieee754.h"
/* /*
* Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when * Emulate the arbitrary instruction ir at xcp->cp0_epc. Required when
* we have to emulate the instruction in a COP1 branch delay slot. Do * we have to emulate the instruction in a COP1 branch delay slot. Do
* not change cp0_epc due to the instruction * not change cp0_epc due to the instruction
* *
@ -88,7 +88,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
fr = (struct emuframe __user *) fr = (struct emuframe __user *)
((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
/* Verify that the stack pointer is not competely insane */ /* Verify that the stack pointer is not completely insane */
if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe)))) if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe))))
return SIGBUS; return SIGBUS;

22
arch/mips/mm/tlbex.c
View File

@ -2361,8 +2361,9 @@ static void print_htw_config(void)
(config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
config = read_c0_pwsize(); config = read_c0_pwsize();
pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
field, config, field, config,
(config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT,
(config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
(config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
(config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
@ -2370,9 +2371,12 @@ static void print_htw_config(void)
(config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
pwctl = read_c0_pwctl(); pwctl = read_c0_pwctl();
pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
pwctl, pwctl,
(pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
(pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT,
(pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT,
(pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT,
(pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
(pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
(pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
@ -2427,15 +2431,25 @@ static void config_htw_params(void)
if (CONFIG_PGTABLE_LEVELS >= 3) if (CONFIG_PGTABLE_LEVELS >= 3)
pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
pwsize |= ilog2(sizeof(pte_t)/4) << MIPS_PWSIZE_PTEW_SHIFT; /* Set pointer size to size of directory pointers */
if (config_enabled(CONFIG_64BIT))
pwsize |= MIPS_PWSIZE_PS_MASK;
/* PTEs may be multiple pointers long (e.g. with XPA) */
pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)
& MIPS_PWSIZE_PTEW_MASK;
write_c0_pwsize(pwsize); write_c0_pwsize(pwsize);
/* Make sure everything is set before we enable the HTW */ /* Make sure everything is set before we enable the HTW */
back_to_back_c0_hazard(); back_to_back_c0_hazard();
/* Enable HTW and disable the rest of the pwctl fields */ /*
* Enable HTW (and only for XUSeg on 64-bit), and disable the rest of
* the pwctl fields.
*/
config = 1 << MIPS_PWCTL_PWEN_SHIFT; config = 1 << MIPS_PWCTL_PWEN_SHIFT;
if (config_enabled(CONFIG_64BIT))
config |= MIPS_PWCTL_XU_MASK;
write_c0_pwctl(config); write_c0_pwctl(config);
pr_info("Hardware Page Table Walker enabled\n"); pr_info("Hardware Page Table Walker enabled\n");

2
arch/mips/oprofile/op_impl.h
View File

@ -24,7 +24,7 @@ struct op_counter_config {
unsigned long unit_mask; unsigned long unit_mask;
}; };
/* Per-architecture configury and hooks. */ /* Per-architecture configure and hooks. */
struct op_mips_model { struct op_mips_model {
void (*reg_setup) (struct op_counter_config *); void (*reg_setup) (struct op_counter_config *);
void (*cpu_setup) (void *dummy); void (*cpu_setup) (void *dummy);

4
arch/mips/pci/ops-bridge.c
View File

@ -33,9 +33,9 @@ static u32 emulate_ioc3_cfg(int where, int size)
* The Bridge ASIC supports both type 0 and type 1 access. Type 1 is * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
* not really documented, so right now I can't write code which uses it. * not really documented, so right now I can't write code which uses it.
* Therefore we use type 0 accesses for now even though they won't work * Therefore we use type 0 accesses for now even though they won't work
* correcly for PCI-to-PCI bridges. * correctly for PCI-to-PCI bridges.
* *
* The function is complicated by the ultimate brokeness of the IOC3 chip * The function is complicated by the ultimate brokenness of the IOC3 chip
* which is used in SGI systems. The IOC3 can only handle 32-bit PCI * which is used in SGI systems. The IOC3 can only handle 32-bit PCI
* accesses and does only decode parts of it's address space. * accesses and does only decode parts of it's address space.
*/ */

8
arch/mips/pistachio/init.c
View File

@ -83,12 +83,16 @@ static void __init plat_setup_iocoherency(void)
} }
} }
void __init plat_mem_setup(void) void __init *plat_get_fdt(void)
{ {
if (fw_arg0 != -2) if (fw_arg0 != -2)
panic("Device-tree not present"); panic("Device-tree not present");
return (void *)fw_arg1;
}
__dt_setup_arch((void *)fw_arg1); void __init plat_mem_setup(void)
{
__dt_setup_arch(plat_get_fdt());
plat_setup_iocoherency(); plat_setup_iocoherency();
} }

112
arch/mips/ralink/mt7620.c
View File

@ -188,6 +188,41 @@ static struct rt2880_pmx_func gpio_grp_mt7628[] = {
FUNC("gpio", 0, 11, 1), FUNC("gpio", 0, 11, 1),
}; };
static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = {
FUNC("jtag", 3, 30, 1),
FUNC("util", 2, 30, 1),
FUNC("gpio", 1, 30, 1),
FUNC("p4led_kn", 0, 30, 1),
};
static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = {
FUNC("jtag", 3, 31, 1),
FUNC("util", 2, 31, 1),
FUNC("gpio", 1, 31, 1),
FUNC("p3led_kn", 0, 31, 1),
};
static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = {
FUNC("jtag", 3, 32, 1),
FUNC("util", 2, 32, 1),
FUNC("gpio", 1, 32, 1),
FUNC("p2led_kn", 0, 32, 1),
};
static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = {
FUNC("jtag", 3, 33, 1),
FUNC("util", 2, 33, 1),
FUNC("gpio", 1, 33, 1),
FUNC("p1led_kn", 0, 33, 1),
};
static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = {
FUNC("jtag", 3, 34, 1),
FUNC("rsvd", 2, 34, 1),
FUNC("gpio", 1, 34, 1),
FUNC("p0led_kn", 0, 34, 1),
};
static struct rt2880_pmx_func wled_kn_grp_mt7628[] = { static struct rt2880_pmx_func wled_kn_grp_mt7628[] = {
FUNC("rsvd", 3, 35, 1), FUNC("rsvd", 3, 35, 1),
FUNC("rsvd", 2, 35, 1), FUNC("rsvd", 2, 35, 1),
@ -195,16 +230,61 @@ static struct rt2880_pmx_func wled_kn_grp_mt7628[] = {
FUNC("wled_kn", 0, 35, 1), FUNC("wled_kn", 0, 35, 1),
}; };
static struct rt2880_pmx_func p4led_an_grp_mt7628[] = {
FUNC("jtag", 3, 39, 1),
FUNC("util", 2, 39, 1),
FUNC("gpio", 1, 39, 1),
FUNC("p4led_an", 0, 39, 1),
};
static struct rt2880_pmx_func p3led_an_grp_mt7628[] = {
FUNC("jtag", 3, 40, 1),
FUNC("util", 2, 40, 1),
FUNC("gpio", 1, 40, 1),
FUNC("p3led_an", 0, 40, 1),
};
static struct rt2880_pmx_func p2led_an_grp_mt7628[] = {
FUNC("jtag", 3, 41, 1),
FUNC("util", 2, 41, 1),
FUNC("gpio", 1, 41, 1),
FUNC("p2led_an", 0, 41, 1),
};
static struct rt2880_pmx_func p1led_an_grp_mt7628[] = {
FUNC("jtag", 3, 42, 1),
FUNC("util", 2, 42, 1),
FUNC("gpio", 1, 42, 1),
FUNC("p1led_an", 0, 42, 1),
};
static struct rt2880_pmx_func p0led_an_grp_mt7628[] = {
FUNC("jtag", 3, 43, 1),
FUNC("rsvd", 2, 43, 1),
FUNC("gpio", 1, 43, 1),
FUNC("p0led_an", 0, 43, 1),
};
static struct rt2880_pmx_func wled_an_grp_mt7628[] = { static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
FUNC("rsvd", 3, 35, 1), FUNC("rsvd", 3, 44, 1),
FUNC("rsvd", 2, 35, 1), FUNC("rsvd", 2, 44, 1),
FUNC("gpio", 1, 35, 1), FUNC("gpio", 1, 44, 1),
FUNC("wled_an", 0, 35, 1), FUNC("wled_an", 0, 44, 1),
}; };
#define MT7628_GPIO_MODE_MASK 0x3 #define MT7628_GPIO_MODE_MASK 0x3
#define MT7628_GPIO_MODE_P4LED_KN 58
#define MT7628_GPIO_MODE_P3LED_KN 56
#define MT7628_GPIO_MODE_P2LED_KN 54
#define MT7628_GPIO_MODE_P1LED_KN 52
#define MT7628_GPIO_MODE_P0LED_KN 50
#define MT7628_GPIO_MODE_WLED_KN 48 #define MT7628_GPIO_MODE_WLED_KN 48
#define MT7628_GPIO_MODE_P4LED_AN 42
#define MT7628_GPIO_MODE_P3LED_AN 40
#define MT7628_GPIO_MODE_P2LED_AN 38
#define MT7628_GPIO_MODE_P1LED_AN 36
#define MT7628_GPIO_MODE_P0LED_AN 34
#define MT7628_GPIO_MODE_WLED_AN 32 #define MT7628_GPIO_MODE_WLED_AN 32
#define MT7628_GPIO_MODE_PWM1 30 #define MT7628_GPIO_MODE_PWM1 30
#define MT7628_GPIO_MODE_PWM0 28 #define MT7628_GPIO_MODE_PWM0 28
@ -223,9 +303,9 @@ static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
#define MT7628_GPIO_MODE_GPIO 0 #define MT7628_GPIO_MODE_GPIO 0
static struct rt2880_pmx_group mt7628an_pinmux_data[] = { static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_PWM1), 1, MT7628_GPIO_MODE_PWM1),
GRP_G("pmw0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_PWM0), 1, MT7628_GPIO_MODE_PWM0),
GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_UART2), 1, MT7628_GPIO_MODE_UART2),
@ -251,8 +331,28 @@ static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
1, MT7628_GPIO_MODE_GPIO), 1, MT7628_GPIO_MODE_GPIO),
GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK, GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_WLED_AN), 1, MT7628_GPIO_MODE_WLED_AN),
GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P0LED_AN),
GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P1LED_AN),
GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P2LED_AN),
GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P3LED_AN),
GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P4LED_AN),
GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_WLED_KN), 1, MT7628_GPIO_MODE_WLED_KN),
GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P0LED_KN),
GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P1LED_KN),
GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P2LED_KN),
GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P3LED_KN),
GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
1, MT7628_GPIO_MODE_P4LED_KN),
{ 0 } { 0 }
}; };

2
arch/mips/sgi-ip27/ip27-hubio.c
View File

@ -105,7 +105,7 @@ static void hub_setup_prb(nasid_t nasid, int prbnum, int credits)
prb.iprb_ff = force_fire_and_forget ? 1 : 0; prb.iprb_ff = force_fire_and_forget ? 1 : 0;
/* /*
* Set the appropriate number of PIO cresits for the widget. * Set the appropriate number of PIO credits for the widget.
*/ */
prb.iprb_xtalkctr = credits; prb.iprb_xtalkctr = credits;

2
arch/mips/sgi-ip27/ip27-nmi.c
View File

@ -23,7 +23,7 @@ typedef unsigned long machreg_t;
static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED; static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED;
/* /*
* Lets see what else we need to do here. Set up sp, gp? * Let's see what else we need to do here. Set up sp, gp?
*/ */
void nmi_dump(void) void nmi_dump(void)
{ {

2
arch/mips/sgi-ip27/ip27-xtalk.c
View File

@ -67,7 +67,7 @@ static int xbow_probe(nasid_t nasid)
return -ENODEV; return -ENODEV;
/* /*
* Okay, here's a xbow. Lets arbitrate and find * Okay, here's a xbow. Let's arbitrate and find
* out if we should initialize it. Set enabled * out if we should initialize it. Set enabled
* hub connected at highest or lowest widget as * hub connected at highest or lowest widget as
* master. * master.

2
arch/mips/sni/rm200.c
View File

@ -263,7 +263,7 @@ void sni_rm200_mask_and_ack_8259A(struct irq_data *d)
static int spurious_irq_mask; static int spurious_irq_mask;
/* /*
* At this point we can be sure the IRQ is spurious, * At this point we can be sure the IRQ is spurious,
* lets ACK and report it. [once per IRQ] * let's ACK and report it. [once per IRQ]
*/ */
if (!(spurious_irq_mask & irqmask)) { if (!(spurious_irq_mask & irqmask)) {
printk(KERN_DEBUG printk(KERN_DEBUG

4
arch/mips/vdso/Makefile
View File

@ -5,10 +5,12 @@ obj-vdso-y := elf.o gettimeofday.o sigreturn.o
ccflags-vdso := \ ccflags-vdso := \
$(filter -I%,$(KBUILD_CFLAGS)) \ $(filter -I%,$(KBUILD_CFLAGS)) \
$(filter -E%,$(KBUILD_CFLAGS)) \ $(filter -E%,$(KBUILD_CFLAGS)) \
$(filter -mmicromips,$(KBUILD_CFLAGS)) \
$(filter -march=%,$(KBUILD_CFLAGS)) $(filter -march=%,$(KBUILD_CFLAGS))
cflags-vdso := $(ccflags-vdso) \ cflags-vdso := $(ccflags-vdso) \
$(filter -W%,$(filter-out -Wa$(comma)%,$(KBUILD_CFLAGS))) \ $(filter -W%,$(filter-out -Wa$(comma)%,$(KBUILD_CFLAGS))) \
-O2 -g -fPIC -fno-common -fno-builtin -G 0 -DDISABLE_BRANCH_PROFILING \ -O2 -g -fPIC -fno-strict-aliasing -fno-common -fno-builtin -G 0 \
-DDISABLE_BRANCH_PROFILING \
$(call cc-option, -fno-stack-protector) $(call cc-option, -fno-stack-protector)
aflags-vdso := $(ccflags-vdso) \ aflags-vdso := $(ccflags-vdso) \
$(filter -I%,$(KBUILD_CFLAGS)) \ $(filter -I%,$(KBUILD_CFLAGS)) \

2
arch/mips/vr41xx/common/cmu.c
View File

@ -3,7 +3,7 @@
* *
* Copyright (C) 2001-2002 MontaVista Software Inc. * Copyright (C) 2001-2002 MontaVista Software Inc.
* Author: Yoichi Yuasa <source@mvista.com> * Author: Yoichi Yuasa <source@mvista.com>
* Copuright (C) 2003-2005 Yoichi Yuasa <yuasa@linux-mips.org> * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@linux-mips.org>
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by

10
drivers/irqchip/irq-mips-gic.c
View File

@ -968,7 +968,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
unsigned int cpu_vec, unsigned int irqbase, unsigned int cpu_vec, unsigned int irqbase,
struct device_node *node) struct device_node *node)
{ {
unsigned int gicconfig; unsigned int gicconfig, cpu;
unsigned int v[2]; unsigned int v[2];
__gic_base_addr = gic_base_addr; __gic_base_addr = gic_base_addr;
@ -985,6 +985,14 @@ static void __init __gic_init(unsigned long gic_base_addr,
gic_vpes = gic_vpes + 1; gic_vpes = gic_vpes + 1;
if (cpu_has_veic) { if (cpu_has_veic) {
/* Set EIC mode for all VPEs */
for_each_present_cpu(cpu) {
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
mips_cm_vp_id(cpu));
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_CTL),
GIC_VPE_CTL_EIC_MODE_MSK);
}
/* Always use vector 1 in EIC mode */ /* Always use vector 1 in EIC mode */
gic_cpu_pin = 0; gic_cpu_pin = 0;
timer_cpu_pin = gic_cpu_pin; timer_cpu_pin = gic_cpu_pin;