openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay 

There is nothing RX-specific about these clock skew values. So remove
"RX" from the name in preparation for the next patch where TX delays are
also going to be configured.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vladimir Oltean 2020-03-19 23:16:46 +02:00 committed by David S. Miller
parent 69ccaf2590
commit 4035e81224
2 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/net/phy/mscc/mscc.h
View File

@ -12,15 +12,15 @@
#include "mscc_macsec.h"
#endif
enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_0_2_NS = 0,
RGMII_RX_CLK_DELAY_0_8_NS = 1,
RGMII_RX_CLK_DELAY_1_1_NS = 2,
RGMII_RX_CLK_DELAY_1_7_NS = 3,
RGMII_RX_CLK_DELAY_2_0_NS = 4,
RGMII_RX_CLK_DELAY_2_3_NS = 5,
RGMII_RX_CLK_DELAY_2_6_NS = 6,
RGMII_RX_CLK_DELAY_3_4_NS = 7
enum rgmii_clock_delay {
RGMII_CLK_DELAY_0_2_NS = 0,
RGMII_CLK_DELAY_0_8_NS = 1,
RGMII_CLK_DELAY_1_1_NS = 2,
RGMII_CLK_DELAY_1_7_NS = 3,
RGMII_CLK_DELAY_2_0_NS = 4,
RGMII_CLK_DELAY_2_3_NS = 5,
RGMII_CLK_DELAY_2_6_NS = 6,
RGMII_CLK_DELAY_3_4_NS = 7
};
/* Microsemi VSC85xx PHY registers */

2
drivers/net/phy/mscc/mscc_main.c
View File

@ -525,7 +525,7 @@ static int vsc85xx_default_config(struct phy_device *phydev)
phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
mutex_lock(&phydev->lock);
reg_val = RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;
reg_val = RGMII_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;
rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK,