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perf, x86: Fix key indexing in Pentium-4 PMU 

Index 0-6 in p4_templates are reserved for common hardware
events. So p4_templates is arranged as below:

    0  -    6:  common hardware events
    7  -    N:  cache events
  N+1  -  ...:  other raw events

Reported-by: Cyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Acked-by: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: Peter Zijlstra <peterz@infradead.org>
LKML-Reference: <1268983738.13901.142.camel@minggr.sh.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Lin Ming 2010-03-19 15:28:58 +08:00 committed by Ingo Molnar
parent 9c8c6bad31
commit 40b7e05e17
1 changed files with 1 additions and 1 deletions
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2
arch/x86/include/asm/perf_event_p4.h
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@ -709,7 +709,7 @@ enum P4_EVENTS_ATTR {
};
enum {
KEY_P4_L1D_OP_READ_RESULT_MISS,
KEY_P4_L1D_OP_READ_RESULT_MISS = PERF_COUNT_HW_MAX,
KEY_P4_LL_OP_READ_RESULT_MISS,
KEY_P4_DTLB_OP_READ_RESULT_MISS,
KEY_P4_DTLB_OP_WRITE_RESULT_MISS,