mirror of https://gitee.com/openkylin/linux.git
ARM: entry: data abort: ensure r5 is preserved by abort functions
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
108f6af0a8
commit
40f0b90a2f
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@ -7,11 +7,7 @@
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* : r4 = aborted context pc
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* : r5 = aborted context psr
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*
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r2-r8 = corrupted
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* : r9 = preserved
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* : sp = pointer to registers
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* Returns : r4-r5, r10-r11, r13 preserved
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*
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* Purpose : obtain information about current aborted instruction.
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* Note: we read user space. This means we might cause a data
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@ -72,30 +68,30 @@ ENTRY(v4t_late_abort)
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add r6, r6, r6, lsr #8
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add r6, r6, r6, lsr #4
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and r6, r6, #15 @ r6 = no. of registers to transfer.
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
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and r9, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6, lsl #2 @ Undo increment
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addeq r7, r7, r6, lsl #2 @ Undo decrement
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str r7, [r2, r5, lsr #14] @ Put register 'Rn'
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str r7, [r2, r9, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_lateldrhpre:
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tst r8, #1 << 21 @ Check writeback bit
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beq do_DataAbort @ No writeback -> no fixup
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.data_arm_lateldrhpost:
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and r5, r8, #0x00f @ get Rm / low nibble of immediate value
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and r9, r8, #0x00f @ get Rm / low nibble of immediate value
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tst r8, #1 << 22 @ if (immediate offset)
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andne r6, r8, #0xf00 @ { immediate high nibble
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orrne r6, r5, r6, lsr #4 @ combine nibbles } else
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ldreq r6, [r2, r5, lsl #2] @ { load Rm value }
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orrne r6, r9, r6, lsr #4 @ combine nibbles } else
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ldreq r6, [r2, r9, lsl #2] @ { load Rm value }
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.data_arm_apply_r6_and_rn:
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
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and r9, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6 @ Undo incrmenet
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addeq r7, r7, r6 @ Undo decrement
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str r7, [r2, r5, lsr #14] @ Put register 'Rn'
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str r7, [r2, r9, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_lateldrpreconst:
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@ -104,12 +100,12 @@ ENTRY(v4t_late_abort)
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.data_arm_lateldrpostconst:
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movs r6, r8, lsl #20 @ Get offset
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beq do_DataAbort @ zero -> no fixup
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
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and r9, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6, lsr #20 @ Undo increment
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addeq r7, r7, r6, lsr #20 @ Undo decrement
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str r7, [r2, r5, lsr #14] @ Put register 'Rn'
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str r7, [r2, r9, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_lateldrprereg:
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@ -118,14 +114,14 @@ ENTRY(v4t_late_abort)
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.data_arm_lateldrpostreg:
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and r7, r8, #15 @ Extract 'm' from instruction
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ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
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mov r5, r8, lsr #7 @ get shift count
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ands r5, r5, #31
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mov r9, r8, lsr #7 @ get shift count
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ands r9, r9, #31
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and r7, r8, #0x70 @ get shift type
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orreq r7, r7, #8 @ shift count = 0
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add pc, pc, r7
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nop
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mov r6, r6, lsl r5 @ 0: LSL #!0
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mov r6, r6, lsl r9 @ 0: LSL #!0
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b .data_arm_apply_r6_and_rn
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b .data_arm_apply_r6_and_rn @ 1: LSL #0
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nop
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@ -133,7 +129,7 @@ ENTRY(v4t_late_abort)
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nop
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b .data_unknown @ 3: MUL?
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nop
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mov r6, r6, lsr r5 @ 4: LSR #!0
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mov r6, r6, lsr r9 @ 4: LSR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, lsr #32 @ 5: LSR #32
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b .data_arm_apply_r6_and_rn
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@ -141,7 +137,7 @@ ENTRY(v4t_late_abort)
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nop
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b .data_unknown @ 7: MUL?
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nop
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mov r6, r6, asr r5 @ 8: ASR #!0
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mov r6, r6, asr r9 @ 8: ASR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, asr #32 @ 9: ASR #32
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b .data_arm_apply_r6_and_rn
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@ -149,7 +145,7 @@ ENTRY(v4t_late_abort)
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nop
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b .data_unknown @ B: MUL?
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nop
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mov r6, r6, ror r5 @ C: ROR #!0
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mov r6, r6, ror r9 @ C: ROR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, rrx @ D: RRX
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b .data_arm_apply_r6_and_rn
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@ -216,9 +212,9 @@ ENTRY(v4t_late_abort)
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and r6, r6, #0x33
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add r6, r6, r9, lsr #2
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add r6, r6, r6, lsr #4
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and r5, r8, #7 << 8
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ldr r7, [r2, r5, lsr #6]
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and r9, r8, #7 << 8
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ldr r7, [r2, r9, lsr #6]
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and r6, r6, #15 @ number of regs to transfer
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sub r7, r7, r6, lsl #2 @ always decrement
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str r7, [r2, r5, lsr #6]
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str r7, [r2, r9, lsr #6]
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b do_DataAbort
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@ -35,8 +35,7 @@ ENTRY(cpu_arm7_dcache_clean_area)
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*
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* Purpose : obtain information about current aborted instruction
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*
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* Returns : r0 = address of abort
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* : r1 = FSR
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* Returns : r4-r5, r10-r11, r13 preserved
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*/
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ENTRY(cpu_arm7_data_abort)
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@ -95,21 +94,21 @@ ENTRY(cpu_arm6_data_abort)
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add r6, r6, r6, lsr #8
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add r6, r6, r6, lsr #4
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and r6, r6, #15 @ r6 = no. of registers to transfer.
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
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and r9, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6, lsl #2 @ Undo increment
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addeq r7, r7, r6, lsl #2 @ Undo decrement
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str r7, [r2, r5, lsr #14] @ Put register 'Rn'
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str r7, [r2, r9, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_apply_r6_and_rn:
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
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and r9, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6 @ Undo incrmenet
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addeq r7, r7, r6 @ Undo decrement
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str r7, [r2, r5, lsr #14] @ Put register 'Rn'
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str r7, [r2, r9, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_lateldrpreconst:
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@ -118,12 +117,12 @@ ENTRY(cpu_arm6_data_abort)
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.data_arm_lateldrpostconst:
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movs r6, r8, lsl #20 @ Get offset
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beq do_DataAbort @ zero -> no fixup
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
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and r9, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6, lsr #20 @ Undo increment
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addeq r7, r7, r6, lsr #20 @ Undo decrement
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str r7, [r2, r5, lsr #14] @ Put register 'Rn'
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str r7, [r2, r9, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_lateldrprereg:
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@ -132,14 +131,14 @@ ENTRY(cpu_arm6_data_abort)
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.data_arm_lateldrpostreg:
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and r7, r8, #15 @ Extract 'm' from instruction
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ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
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mov r5, r8, lsr #7 @ get shift count
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ands r5, r5, #31
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mov r9, r8, lsr #7 @ get shift count
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ands r9, r9, #31
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and r7, r8, #0x70 @ get shift type
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orreq r7, r7, #8 @ shift count = 0
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add pc, pc, r7
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nop
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mov r6, r6, lsl r5 @ 0: LSL #!0
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mov r6, r6, lsl r9 @ 0: LSL #!0
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b .data_arm_apply_r6_and_rn
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b .data_arm_apply_r6_and_rn @ 1: LSL #0
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nop
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@ -147,7 +146,7 @@ ENTRY(cpu_arm6_data_abort)
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nop
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b .data_unknown @ 3: MUL?
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nop
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mov r6, r6, lsr r5 @ 4: LSR #!0
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mov r6, r6, lsr r9 @ 4: LSR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, lsr #32 @ 5: LSR #32
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b .data_arm_apply_r6_and_rn
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@ -155,7 +154,7 @@ ENTRY(cpu_arm6_data_abort)
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nop
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b .data_unknown @ 7: MUL?
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nop
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mov r6, r6, asr r5 @ 8: ASR #!0
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mov r6, r6, asr r9 @ 8: ASR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, asr #32 @ 9: ASR #32
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b .data_arm_apply_r6_and_rn
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@ -163,7 +162,7 @@ ENTRY(cpu_arm6_data_abort)
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nop
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b .data_unknown @ B: MUL?
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nop
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mov r6, r6, ror r5 @ C: ROR #!0
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mov r6, r6, ror r9 @ C: ROR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, rrx @ D: RRX
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b .data_arm_apply_r6_and_rn
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