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drm/nouveau/fence: use NVIDIA's headers for sync() 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2020-07-20 11:19:26 +10:00
parent 60cdadace3
commit 40f1171e7c
5 changed files with 39 additions and 36 deletions
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10
drivers/gpu/drm/nouveau/include/nvhw/class/cl176e.h Normal file
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@ -0,0 +1,10 @@
/* SPDX-License-Identifier: MIT */
#ifndef _cl176e_h_
#define _cl176e_h_
#define NV176E_SET_OBJECT (0x00000000)
#define NV176E_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
#define NV176E_SEMAPHORE_OFFSET (0x00000064)
#define NV176E_SEMAPHORE_ACQUIRE (0x00000068)
#define NV176E_SEMAPHORE_RELEASE (0x0000006c)
#endif

14
drivers/gpu/drm/nouveau/nouveau_dma.h
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@ -103,20 +103,6 @@ WIND_RING(struct nouveau_channel *chan)
chan->dma.cur = chan->dma.put;
}
/* FIFO methods */
#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
/* NV_SW object class */
#define NV_SW_DMA_VBLSEM 0x0000018c
#define NV_SW_VBLSEM_OFFSET 0x00000400

18
drivers/gpu/drm/nouveau/nv17_fence.c
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@ -30,6 +30,8 @@
#include <nvif/class.h>
#include <nvif/cl0002.h>
#include <nvhw/class/cl176e.h>
int
nv17_fence_sync(struct nouveau_fence *fence,
struct nouveau_channel *prev, struct nouveau_channel *chan)
@ -52,18 +54,18 @@ nv17_fence_sync(struct nouveau_fence *fence,
ret = PUSH_WAIT(ppush, 5);
if (!ret) {
PUSH_NVSQ(ppush, NV176E, NV11_SUBCHAN_DMA_SEMAPHORE, fctx->sema.handle,
NV11_SUBCHAN_SEMAPHORE_OFFSET, 0,
NV11_SUBCHAN_SEMAPHORE_ACQUIRE, value + 0,
NV11_SUBCHAN_SEMAPHORE_RELEASE, value + 1);
PUSH_MTHD(ppush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
SEMAPHORE_OFFSET, 0,
SEMAPHORE_ACQUIRE, value + 0,
SEMAPHORE_RELEASE, value + 1);
PUSH_KICK(ppush);
}
if (!ret && !(ret = PUSH_WAIT(npush, 5))) {
PUSH_NVSQ(npush, NV176E, NV11_SUBCHAN_DMA_SEMAPHORE, fctx->sema.handle,
NV11_SUBCHAN_SEMAPHORE_OFFSET, 0,
NV11_SUBCHAN_SEMAPHORE_ACQUIRE, value + 1,
NV11_SUBCHAN_SEMAPHORE_RELEASE, value + 2);
PUSH_MTHD(npush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
SEMAPHORE_OFFSET, 0,
SEMAPHORE_ACQUIRE, value + 1,
SEMAPHORE_RELEASE, value + 2);
PUSH_KICK(npush);
}

17
drivers/gpu/drm/nouveau/nv84_fence.c
View File

@ -61,13 +61,16 @@ nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
struct nvif_push *push = chan->chan.push;
int ret = PUSH_WAIT(push, 7);
if (ret == 0) {
PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle);
PUSH_NVSQ(push, NV826F,
NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
NV84_SUBCHAN_SEMAPHORE_TRIGGER,
NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
PUSH_MTHD(push, NV826F, SEMAPHOREA,
NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
SEMAPHOREB, lower_32_bits(virtual),
SEMAPHOREC, sequence,
SEMAPHORED,
NVDEF(NV826F, SEMAPHORED, OPERATION, ACQ_GEQ));
PUSH_KICK(push);
}
return ret;

16
drivers/gpu/drm/nouveau/nvc0_fence.c
View File

@ -60,13 +60,15 @@ nvc0_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
struct nvif_push *push = chan->chan.push;
int ret = PUSH_WAIT(push, 5);
if (ret == 0) {
PUSH_NVSQ(push, NV906F,
NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
NV84_SUBCHAN_SEMAPHORE_TRIGGER,
NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
PUSH_MTHD(push, NV906F, SEMAPHOREA,
NVVAL(NV906F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
SEMAPHOREB, lower_32_bits(virtual),
SEMAPHOREC, sequence,
SEMAPHORED,
NVDEF(NV906F, SEMAPHORED, OPERATION, ACQ_GEQ) |
NVDEF(NV906F, SEMAPHORED, ACQUIRE_SWITCH, ENABLED));
PUSH_KICK(push);
}
return ret;