openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

The i.MX device tree updates for 4.7: 

- More i.MX6 System-on-Module board support from Ka-Ro electronics:
    tx6s-8xxx, tx6u-8xxx, tx6q-1xxx, tx6ul-00xx.
  - Nitrogen6_MAX QP and Nitrogen6_SoloX board support from Boundary
    Devices.
  - VF610 based ZII development board support.
  - Add SAI interface audio support for i.MX6SX SDB board.
  - A number of random updates on LS1021A and VF610 dts files.
  - A couple of pinumx updates on i.MX25 and i.MX28.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJXFHWaAAoJEFBXWFqHsHzOIVYH/j6uTUwEa5Ez5j933SDtPd16
 fzL43h7WmMUUgKD4UlOyCSvsfILY5QfkVjEgneeYkBtxZA7T6YYpWE7SeNgjbqtW
 GURIkWOf9vi4k0afJIaR44TZjfij2TDwEYO8ySPfjgrmtX7bJUtB0WxyiqrycSYh
 ibJXnqGfhRxF3Htu+NBrp+NSgreBSqR+SXKQoP/xqzyKFDaFa3msL1YPIRIVrInI
 t/bAvhmMfS5Or+0zZNXa0oem3DmnA+jbVmn/nFgzejsIA94c3Zr4yzKD7SvYDEDI
 Ej4rwB40IWc7vNizbvg3xRhinwxbwD1emqPQm8rqxTpXiLrDn6QjCZocKfP+Wg0=
 =c+YT
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

Merge "The i.MX device tree updates for 4.7" from Shawn Guo:

 - More i.MX6 System-on-Module board support from Ka-Ro electronics:
   tx6s-8xxx, tx6u-8xxx, tx6q-1xxx, tx6ul-00xx.
 - Nitrogen6_MAX QP and Nitrogen6_SoloX board support from Boundary
   Devices.
 - VF610 based ZII development board support.
 - Add SAI interface audio support for i.MX6SX SDB board.
 - A number of random updates on LS1021A and VF610 dts files.
 - A couple of pinumx updates on i.MX25 and i.MX28.

* tag 'imx-dt-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (36 commits)
  ARM: dts: imx6qdl-udoo: add 7 inch LCD touchscreen panel support
  ARM: dts: i.MX3x: add keypad port devicetree nodes
  ARM: dts: ls1021a: add pix clock to DCU dts node
  ARM: dts: ls1021a: DSPI has 6 chip-selects
  ARM: dts: ls1021a: Add gpio support for ls1021a platform
  ARM: dts: imx6q-ba16: Remove unused vqmmc-supply
  ARM: dts: ls1021a: add SCFG MSI dts node
  ARM: dts: imx28: add alternative pinmuxing for mac0
  ARM: dts: imx6q-tbs2910: fix fec reset polarity
  ARM: dts: vf610-zii-dev: Add ZII development board.
  ARM: dts: vfxxx: add missing reg properties
  ARM: dts: vf-colibri: increase NAND clock speed
  ARM: dts: vf-colibri: alias the primary FEC as ethernet0
  ARM: dts: imx6sx-sdb: Add SAI support
  bindings: fsl-imx-sdma: Document 'fsl,sdma-event-remap' property
  ARM: dts: imx6sx: Remove unused property
  ARM: dts: imx6sx: Fix SAI DMA index
  ARM: dts: imx6q-ba16: Disable pwm2 by default
  ARM: dts: imx: add Boundary Devices Nitrogen6_SoloX board
  ARM: dts: imx6qdl-sabresd: Pass the hannstar panel compatible string
  ...
This commit is contained in:
Arnd Bergmann 2016-04-24 23:36:10 +02:00
parent a5cc8c3a71 880e1509db
commit 412252ac8c
41 changed files with 5558 additions and 555 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
View File

@ -58,6 +58,15 @@ The third cell specifies the transfer priority as below.
1 Medium
2 Low
Optional properties:
- gpr : The phandle to the General Purpose Register (GPR) node.
- fsl,sdma-event-remap : Register bits of sdma event remap, the format is
<reg shift val>.
reg is the GPR register offset.
shift is the bit position inside the GPR register.
val is the value of the bit (0 or 1).
Examples:
sdma@83fb0000 {
@ -83,3 +92,21 @@ ssi2: ssi@70014000 {
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
};
Using the fsl,sdma-event-remap property:
If we want to use SDMA on the SAI1 port on a MX6SX:
&sdma {
gpr = <&gpr>;
/* SDMA events remap for SAI1_RX and SAI1_TX */
fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
};
The fsl,sdma-event-remap property in this case has two values:
- <0 15 1> means that the offset is 0, so GPR0 is the register of the
SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
Setting bit 15 to 1 selects SAI1_RX.
- <0 16 1> means that the offset is 0, so GPR0 is the register of the
SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
Setting bit 16 to 1 selects SAI1_TX.

17
arch/arm/boot/dts/Makefile
View File

@ -324,8 +324,12 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-sabrelite.dtb \
imx6dl-sabresd.dtb \
imx6dl-tx6dl-comtft.dtb \
imx6dl-tx6s-8034.dtb \
imx6dl-tx6s-8035.dtb \
imx6dl-tx6u-801x.dtb \
imx6dl-tx6u-8033.dtb \
imx6dl-tx6u-811x.dtb \
imx6dl-tx6u-81xx-mb7.dtb \
imx6dl-udoo.dtb \
imx6dl-wandboard.dtb \
imx6dl-wandboard-revb1.dtb \
@ -364,21 +368,29 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-tx6q-1010-comtft.dtb \
imx6q-tx6q-1020.dtb \
imx6q-tx6q-1020-comtft.dtb \
imx6q-tx6q-1036.dtb \
imx6q-tx6q-1110.dtb \
imx6q-tx6q-11x0-mb7.dtb \
imx6q-udoo.dtb \
imx6q-wandboard.dtb \
imx6q-wandboard-revb1.dtb \
imx6qp-nitrogen6_max.dtb \
imx6qp-sabreauto.dtb \
imx6qp-sabresd.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-nitrogen6sx.dtb \
imx6sx-sabreauto.dtb \
imx6sx-sdb-reva.dtb \
imx6sx-sdb-sai.dtb \
imx6sx-sdb.dtb
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb
imx6ul-14x14-evk.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-sbc-imx7.dtb \
@ -392,7 +404,8 @@ dtb-$(CONFIG_SOC_VF610) += \
vf610m4-colibri.dtb \
vf610-cosmic.dtb \
vf610m4-cosmic.dtb \
vf610-twr.dtb
vf610-twr.dtb \
vf610-zii-dev-rev-b.dtb
dtb-$(CONFIG_ARCH_MXS) += \
imx23-evk.dtb \
imx23-olinuxino.dtb \

124
arch/arm/boot/dts/imx25-pinfunc.h
View File

@ -110,20 +110,20 @@
#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x13 0x000
#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x15 0x000
#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x10 0x000
#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000
#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000
#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x13 0x000
#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x15 0x000
#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000
#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000
#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x10 0x000
#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x15 0x000
#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x10 0x000
#define MX25_PAD_ECB__UART5_TXD_MUX 0x060 0x270 0x000 0x13 0x000
#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x13 0x000
#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x15 0x000
#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x10 0x000
#define MX25_PAD_LBA__UART5_RXD_MUX 0x064 0x274 0x578 0x13 0x000
#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x13 0x000
#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x15 0x000
#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000
@ -237,17 +237,21 @@
#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x15 0x000
#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000
#define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x12 0x000
#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000
#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000
#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000
#define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x12 0x000
#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001
#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000
#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000
#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x15 0x001
#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000
#define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000
#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x05 0x001
#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000
#define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x12 0x000
#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001
#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000
@ -291,22 +295,22 @@
#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x16 0x001
#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000
#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001
#define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x11 0x001
#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000
#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000
#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000
#define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x11 0x000
#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000
#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000
#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001
#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x00 0x000
#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001
#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000
#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000
#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000
#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x07 0x000
#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x000
@ -360,7 +364,7 @@
#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000
#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000
#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x000 0x12 0x000
#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x568 0x12 0x000
#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000
#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000
@ -371,10 +375,10 @@
#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x12 0x000
#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x11 0x001
#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x12 0x000
#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x00 0x000
#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x01 0x001
#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x02 0x000
#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x05 0x000
#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x12 0x000
@ -383,20 +387,24 @@
#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000
#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x15 0x000
#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x10 0x000
#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x15 0x000
#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x00 0x000
#define MX25_PAD_UART1_RXD__UART2_DTR 0x170 0x368 0x000 0x03 0x000
#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x05 0x000
#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x10 0x000
#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x15 0x000
#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x00 0x000
#define MX25_PAD_UART1_TXD__UART2_DSR 0x174 0x36c 0x000 0x03 0x000
#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x05 0x000
#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000
#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001
#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x12 0x000
#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000
#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000
#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001
#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x02 0x000
#define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000
#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000
#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000
#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x11 0x001
#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x15 0x000
#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x00 0x000
#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x01 0x001
#define MX25_PAD_UART1_CTS__UART2_RI 0x17c 0x374 0x000 0x03 0x001
#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x05 0x000
#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x10 0x000
#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x15 0x000
@ -404,10 +412,10 @@
#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x10 0x000
#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x15 0x000
#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000
#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002
#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000
#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000
#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002
#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x03 0x000
#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000
#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000
#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x12 0x002
@ -439,36 +447,42 @@
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x12 0x002
#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW0__UART1_DTR 0x1a8 0x3a0 0x000 0x14 0x000
#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x00 0x000
#define MX25_PAD_KPP_ROW0__UART3_RXD 0x1a8 0x3a0 0x568 0x01 0x001
#define MX25_PAD_KPP_ROW0__UART1_DTR 0x1a8 0x3a0 0x000 0x04 0x000
#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x05 0x000
#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x00 0x000
#define MX25_PAD_KPP_ROW1__UART3_TXD 0x1ac 0x3a4 0x000 0x01 0x000
#define MX25_PAD_KPP_ROW1__UART1_DSR 0x1ac 0x3a4 0x000 0x04 0x000
#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x05 0x000
#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x13 0x002
#define MX25_PAD_KPP_ROW2__UART1_DCD 0x1b0 0x3a8 0x000 0x14 0x000
#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x00 0x000
#define MX25_PAD_KPP_ROW2__UART3_RTS 0x1b0 0x3a8 0x000 0x01 0x000
#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x03 0x002
#define MX25_PAD_KPP_ROW2__UART1_DCD 0x1b0 0x3a8 0x000 0x04 0x000
#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x05 0x000
#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x13 0x002
#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x00 0x000
#define MX25_PAD_KPP_ROW3__UART3_CTS 0x1b4 0x3ac 0x000 0x01 0x000
#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x03 0x002
#define MX25_PAD_KPP_ROW3__UART1_RI 0x1b4 0x3ac 0x000 0x04 0x000
#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x05 0x000
#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000
#define MX25_PAD_KPP_COL0__UART4_RXD_MUX 0x1b8 0x3b0 0x570 0x11 0x001
#define MX25_PAD_KPP_COL0__UART4_RXD 0x1b8 0x3b0 0x570 0x11 0x001
#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x12 0x000
#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x15 0x000
#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x10 0x000
#define MX25_PAD_KPP_COL1__UART4_TXD_MUX 0x1bc 0x3b4 0x000 0x11 0x000
#define MX25_PAD_KPP_COL1__UART4_TXD 0x1bc 0x3b4 0x000 0x11 0x000
#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x12 0x000
#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x15 0x000
#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x10 0x000
#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x000 0x11 0x000
#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x12 0x000
#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x15 0x000
#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x00 0x000
#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x56c 0x01 0x001
#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x02 0x000
#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x05 0x000
#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x10 0x000
#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x11 0x000
@ -557,9 +571,10 @@
#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x10 0x000
#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x15 0x000
#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000
#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000
#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000
#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x00 0x000
#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x04 0x000
#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x05 0x000
#define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002
#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000
#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000
@ -567,6 +582,7 @@
#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x10 0x000
#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x14 0x001
#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x15 0x000
#define MX25_PAD_POWER_FAIL__UART4_CTS 0x21c 0x410 0x000 0x16 0x000
#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x10 0x000
#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x15 0x000

26
arch/arm/boot/dts/imx28.dtsi
View File

@ -434,6 +434,32 @@ MX28_PAD_ENET_CLK__CLKCTRL_ENET
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mac0_pins_b: mac0@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_ENET0_MDC__ENET0_MDC
MX28_PAD_ENET0_MDIO__ENET0_MDIO
MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
MX28_PAD_ENET0_RXD0__ENET0_RXD0
MX28_PAD_ENET0_RXD1__ENET0_RXD1
MX28_PAD_ENET0_RXD2__ENET0_RXD2
MX28_PAD_ENET0_RXD3__ENET0_RXD3
MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
MX28_PAD_ENET0_TXD0__ENET0_TXD0
MX28_PAD_ENET0_TXD1__ENET0_TXD1
MX28_PAD_ENET0_TXD2__ENET0_TXD2
MX28_PAD_ENET0_TXD3__ENET0_TXD3
MX28_PAD_ENET_CLK__CLKCTRL_ENET
MX28_PAD_ENET0_COL__ENET0_COL
MX28_PAD_ENET0_CRS__ENET0_CRS
MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mac1_pins_a: mac1@0 {
reg = <0>;
fsl,pinmux-ids = <

8
arch/arm/boot/dts/imx31.dtsi
View File

@ -69,6 +69,14 @@ uart2: serial@43f94000 {
status = "disabled";
};
kpp: kpp@43fa8000 {
compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
reg = <0x43fa8000 0x4000>;
interrupts = <24>;
clocks = <&clks 46>;
status = "disabled";
};
uart4: serial@43fb0000 {
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
reg = <0x43fb0000 0x4000>;

8
arch/arm/boot/dts/imx35.dtsi
View File

@ -137,6 +137,14 @@ spi1: cspi@43fa4000 {
status = "disabled";
};
kpp: kpp@43fa8000 {
compatible = "fsl,imx35-kpp", "fsl,imx21-kpp";
reg = <0x43fa8000 0x4000>;
interrupts = <24>;
clocks = <&clks 56>;
status = "disabled";
};
iomuxc: iomuxc@43fac000 {
compatible = "fsl,imx35-iomuxc";
reg = <0x43fac000 0x4000>;

42
arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts
View File

@ -1,12 +1,42 @@
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

237
arch/arm/boot/dts/imx6dl-tx6s-8034.dts Normal file
View File

@ -0,0 +1,237 @@
/*
* Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6S-8034 Module";
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
aliases {
display = &display;
ipu1 = &ipu1;
};
cpus {
/delete-node/ cpu@1;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd0_pwr>;
enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_lcd1_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
display: display@di0 {
compatible = "fsl,imx-parallel-display";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_2>;
interface-pix-fmt = "rgb24";
status = "okay";
port {
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
display-timings {
native-mode = <&vga>;
vga: VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hsync-len = <96>;
hfront-porch = <16>;
vback-porch = <31>;
vsync-len = <2>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETV570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <114>;
hsync-len = <30>;
hfront-porch = <16>;
vback-porch = <32>;
vsync-len = <3>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0350 {
clock-frequency = <6413760>;
hactive = <320>;
vactive = <240>;
hback-porch = <34>;
hsync-len = <34>;
hfront-porch = <20>;
vback-porch = <15>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0430 {
clock-frequency = <9009000>;
hactive = <480>;
vactive = <272>;
hback-porch = <2>;
hsync-len = <41>;
hfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
vfront-porch = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ET0500 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0700 { /* same as ET0500 */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETQ570 {
clock-frequency = <6596040>;
hactive = <320>;
vactive = <240>;
hback-porch = <38>;
hsync-len = <30>;
hfront-porch = <30>;
vback-porch = <16>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&ds1339 {
status = "disabled";
};
&pinctrl_usdhc1 {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
>;
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&reg_lcd0_pwr {
status = "disabled";
};

253
arch/arm/boot/dts/imx6dl-tx6s-8035.dts Normal file
View File

@ -0,0 +1,253 @@
/*
* Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6S-8035 Module";
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
aliases {
display = &display;
ipu1 = &ipu1;
};
cpus {
/delete-node/ cpu@1;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd0_pwr>;
enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_lcd1_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
display: display@di0 {
compatible = "fsl,imx-parallel-display";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_2>;
interface-pix-fmt = "rgb24";
status = "okay";
port {
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
display-timings {
native-mode = <&vga>;
vga: VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hsync-len = <96>;
hfront-porch = <16>;
vback-porch = <31>;
vsync-len = <2>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETV570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <114>;
hsync-len = <30>;
hfront-porch = <16>;
vback-porch = <32>;
vsync-len = <3>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0350 {
clock-frequency = <6413760>;
hactive = <320>;
vactive = <240>;
hback-porch = <34>;
hsync-len = <34>;
hfront-porch = <20>;
vback-porch = <15>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0430 {
clock-frequency = <9009000>;
hactive = <480>;
vactive = <272>;
hback-porch = <2>;
hsync-len = <41>;
hfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
vfront-porch = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ET0500 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0700 { /* same as ET0500 */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETQ570 {
clock-frequency = <6596040>;
hactive = <320>;
vactive = <240>;
hback-porch = <38>;
hsync-len = <30>;
hfront-porch = <30>;
vback-porch = <16>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&ds1339 {
status = "disabled";
};
&gpmi {
status = "disabled";
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&reg_lcd0_pwr {
status = "disabled";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <4>;
non-removable;
no-1-8-v;
fsl,wp-controller;
status = "okay";
};
&iomuxc {
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
>;
};
};

42
arch/arm/boot/dts/imx6dl-tx6u-801x.dts
View File

@ -1,12 +1,42 @@
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

248
arch/arm/boot/dts/imx6dl-tx6u-8033.dts Normal file
View File

@ -0,0 +1,248 @@
/*
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6U-8033 Module";
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
aliases {
display = &display;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd0_pwr>;
enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_lcd1_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
display: display@di0 {
compatible = "fsl,imx-parallel-display";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_2>;
interface-pix-fmt = "rgb24";
status = "okay";
port {
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
display-timings {
native-mode = <&vga>;
vga: VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hsync-len = <96>;
hfront-porch = <16>;
vback-porch = <31>;
vsync-len = <2>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETV570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <114>;
hsync-len = <30>;
hfront-porch = <16>;
vback-porch = <32>;
vsync-len = <3>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0350 {
clock-frequency = <6413760>;
hactive = <320>;
vactive = <240>;
hback-porch = <34>;
hsync-len = <34>;
hfront-porch = <20>;
vback-porch = <15>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0430 {
clock-frequency = <9009000>;
hactive = <480>;
vactive = <272>;
hback-porch = <2>;
hsync-len = <41>;
hfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
vfront-porch = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ET0500 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0700 { /* same as ET0500 */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETQ570 {
clock-frequency = <6596040>;
hactive = <320>;
vactive = <240>;
hback-porch = <38>;
hsync-len = <30>;
hfront-porch = <30>;
vback-porch = <16>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&ds1339 {
status = "disabled";
};
&gpmi {
status = "disabled";
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&reg_lcd0_pwr {
status = "disabled";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <4>;
non-removable;
no-1-8-v;
fsl,wp-controller;
status = "okay";
};
&iomuxc {
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
>;
};
};

60
arch/arm/boot/dts/imx6dl-tx6u-811x.dts
View File

@ -1,12 +1,42 @@
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@ -81,16 +111,6 @@ polytouch2: eeti@04 {
};
};
&iomuxc {
imx6dl-tx6u-811x {
pinctrl_eeti: eetigrp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
>;
};
};
};
&kpp {
status = "disabled"; /* pad conflict with backlight1 PWM */
};
@ -148,3 +168,11 @@ lvds_timing1: hsd100pxn1 {
&pwm1 {
status = "okay";
};
&iomuxc {
pinctrl_eeti: eetigrp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
>;
};
};

255
arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts Normal file
View File

@ -0,0 +1,255 @@
/*
* Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6U-81xx Module on MB7 baseboard";
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
aliases {
display = &lvds0;
lvds0 = &lvds0;
lvds1 = &lvds1;
};
backlight0: backlight0 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
power-supply = <&reg_lcd0_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
backlight1: backlight1 {
compatible = "pwm-backlight";
pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
power-supply = <&reg_lcd1_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
};
&can1 {
status = "disabled";
};
&can2 {
xceiver-supply = <&reg_3v3>;
};
&i2c3 {
polytouch1: eeti@04 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eeti>;
interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
wakeup-source;
};
};
&kpp {
status = "disabled"; /* pads partially clash with backlight1 PWM */
};
&ldb {
status = "okay";
lvds0: lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&lvds0_timing1>;
lvds0_timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
lvds0_timing1: VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hfront-porch = <16>;
vback-porch = <31>;
vfront-porch = <12>;
hsync-len = <96>;
vsync-len = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
lvds0_timing2: nl12880bc20 {
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <50>;
hfront-porch = <50>;
vback-porch = <5>;
vfront-porch = <5>;
hsync-len = <60>;
vsync-len = <13>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
lvds1: lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&lvds1_timing2>;
lvds1_timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
lvds1_timing1: VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hfront-porch = <16>;
vback-porch = <31>;
vfront-porch = <12>;
hsync-len = <96>;
vsync-len = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
lvds1_timing2: nl12880bc20 {
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <50>;
hfront-porch = <50>;
vback-porch = <5>;
vfront-porch = <5>;
hsync-len = <60>;
vsync-len = <13>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
};
&pwm1 {
status = "okay";
};
&iomuxc {
pinctrl_eeti: eetigrp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
>;
};
};

5
arch/arm/boot/dts/imx6q-ba16.dtsi
View File

@ -323,6 +323,8 @@ &pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
fsl,tx-swing-full = <103>;
fsl,tx-swing-low = <103>;
status = "okay";
};
@ -335,7 +337,7 @@ &pwm1 {
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
status = "disabled";
};
&sata {
@ -390,7 +392,6 @@ &usdhc3 {
pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
bus-width = <8>;
vmmc-supply = <&vdd_bperi>;
vqmmc-supply = <&vdd_bio>;
non-removable;
keep-power-in-suspend;
status = "okay";

2
arch/arm/boot/dts/imx6q-tbs2910.dts
View File

@ -141,7 +141,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
status = "okay";
};

42
arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts
View File

@ -1,12 +1,42 @@
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

42
arch/arm/boot/dts/imx6q-tx6q-1010.dts
View File

@ -1,12 +1,42 @@
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

72
arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts
View File

@ -1,12 +1,42 @@
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@ -94,22 +124,6 @@ &gpmi {
status = "disabled";
};
&iomuxc {
imx6qdl-tx6 {
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
>;
};
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
@ -134,3 +148,17 @@ &usdhc4 {
fsl,wp-controller;
status = "okay";
};
&iomuxc {
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
>;
};
};

72
arch/arm/boot/dts/imx6q-tx6q-1020.dts
View File

@ -1,12 +1,42 @@
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@ -180,22 +210,6 @@ &gpmi {
status = "disabled";
};
&iomuxc {
imx6qdl-tx6 {
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
>;
};
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
@ -208,3 +222,17 @@ &usdhc4 {
fsl,wp-controller;
status = "okay";
};
&iomuxc {
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
>;
};
};

252
arch/arm/boot/dts/imx6q-tx6q-1036.dts Normal file
View File

@ -0,0 +1,252 @@
/*
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6Q-1036 Module";
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
aliases {
display = &display;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd0_pwr>;
enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_lcd1_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
display: display@di0 {
compatible = "fsl,imx-parallel-display";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_2>;
interface-pix-fmt = "rgb24";
status = "okay";
port {
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
display-timings {
native-mode = <&vga>;
vga: VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hsync-len = <96>;
hfront-porch = <16>;
vback-porch = <31>;
vsync-len = <2>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETV570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <114>;
hsync-len = <30>;
hfront-porch = <16>;
vback-porch = <32>;
vsync-len = <3>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0350 {
clock-frequency = <6413760>;
hactive = <320>;
vactive = <240>;
hback-porch = <34>;
hsync-len = <34>;
hfront-porch = <20>;
vback-porch = <15>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0430 {
clock-frequency = <9009000>;
hactive = <480>;
vactive = <272>;
hback-porch = <2>;
hsync-len = <41>;
hfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
vfront-porch = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ET0500 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0700 { /* same as ET0500 */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ETQ570 {
clock-frequency = <6596040>;
hactive = <320>;
vactive = <240>;
hback-porch = <38>;
hsync-len = <30>;
hfront-porch = <30>;
vback-porch = <16>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&ds1339 {
status = "disabled";
};
&gpmi {
status = "disabled";
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&ipu2 {
status = "disabled";
};
&reg_lcd0_pwr {
status = "disabled";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <4>;
non-removable;
no-1-8-v;
fsl,wp-controller;
status = "okay";
};
&iomuxc {
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
>;
};
};

60
arch/arm/boot/dts/imx6q-tx6q-1110.dts
View File

@ -1,12 +1,42 @@
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@ -81,16 +111,6 @@ polytouch1: eeti@04 {
};
};
&iomuxc {
imx6q-tx6q-1110 {
pinctrl_eeti: eetigrp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
>;
};
};
};
&kpp {
status = "disabled"; /* pad conflict with backlight1 PWM */
};
@ -152,3 +172,11 @@ &pwm1 {
&sata {
status = "okay";
};
&iomuxc {
pinctrl_eeti: eetigrp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
>;
};
};

264
arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts Normal file
View File

@ -0,0 +1,264 @@
/*
* Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-tx6.dtsi"
/ {
model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard";
compatible = "karo,imx6q-tx6q", "fsl,imx6q";
aliases {
display = &lvds0;
ipu1 = &ipu2;
lvds0 = &lvds0;
lvds1 = &lvds1;
};
backlight0: backlight0 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
power-supply = <&reg_lcd0_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
backlight1: backlight1 {
compatible = "pwm-backlight";
pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
power-supply = <&reg_lcd1_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
};
&can1 {
status = "disabled";
};
&can2 {
xceiver-supply = <&reg_3v3>;
};
&i2c3 {
polytouch1: eeti@04 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eeti>;
interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
wakeup-source;
};
};
&ipu2 {
status = "disabled";
};
&kpp {
status = "disabled"; /* pads partially clash with backlight1 PWM */
};
&ldb {
status = "okay";
lvds0: lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&lvds0_timing1>;
lvds0_timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
lvds0_timing1: VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hfront-porch = <16>;
vback-porch = <31>;
vfront-porch = <12>;
hsync-len = <96>;
vsync-len = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
lvds0_timing2: nl12880bc20 {
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <50>;
hfront-porch = <50>;
vback-porch = <5>;
vfront-porch = <5>;
hsync-len = <60>;
vsync-len = <13>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
lvds1: lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&lvds1_timing2>;
lvds1_timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
lvds1_timing1: VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hfront-porch = <16>;
vback-porch = <31>;
vfront-porch = <12>;
hsync-len = <96>;
vsync-len = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
lvds1_timing2: nl12880bc20 {
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <50>;
hfront-porch = <50>;
vback-porch = <5>;
vfront-porch = <5>;
hsync-len = <60>;
vsync-len = <13>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
};
&pwm1 {
status = "okay";
};
&sata {
status = "okay";
};
&iomuxc {
pinctrl_eeti: eetigrp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
>;
};
};

30
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View File

@ -115,7 +115,7 @@ sound {
mux-ext-port = <3>;
};
backlight {
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@ -133,6 +133,17 @@ red {
default-state = "on";
};
};
panel {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
};
&audmux {
@ -509,18 +520,11 @@ lvds-channel@1 {
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};

788
arch/arm/boot/dts/imx6qdl-tx6.dtsi
View File

@ -1,12 +1,42 @@
/*
* Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
* Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
@ -37,6 +67,7 @@ memory {
clocks {
#address-cells = <1>;
#size-cells = <0>;
mclk: clock@0 {
compatible = "fixed-clock";
reg = <0>;
@ -61,109 +92,95 @@ leds {
user_led: user {
label = "Heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_user_led>;
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3v3_etn: regulator-3v3-etn {
compatible = "regulator-fixed";
regulator-name = "3V3_ETN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_etnphy_power>;
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_3v3_etn: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3V3_ETN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_etnphy_power>;
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_2v5: regulator-2v5 {
compatible = "regulator-fixed";
regulator-name = "2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_2v5: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_3v3: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_can_xcvr: regulator-can-xcvr {
compatible = "regulator-fixed";
regulator-name = "CAN XCVR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan_xcvr>;
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
enable-active-low;
};
reg_can_xcvr: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "CAN XCVR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan_xcvr>;
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
enable-active-low;
};
reg_lcd0_pwr: regulator-lcd0-pwr {
compatible = "regulator-fixed";
regulator-name = "LCD0 POWER";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd0_pwr>;
gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
reg_lcd0_pwr: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "LCD0 POWER";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd0_pwr>;
gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
};
reg_lcd1_pwr: regulator-lcd1-pwr {
compatible = "regulator-fixed";
regulator-name = "LCD1 POWER";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd1_pwr>;
gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
reg_lcd1_pwr: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "LCD1 POWER";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd1_pwr>;
gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
};
reg_usbh1_vbus: regulator-usbh1-vbus {
compatible = "regulator-fixed";
regulator-name = "usbh1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1_vbus>;
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbh1_vbus: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
regulator-name = "usbh1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1_vbus>;
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg_vbus: regulator@7 {
compatible = "regulator-fixed";
reg = <7>;
regulator-name = "usbotg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_vbus>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg_vbus: regulator-usbotg-vbus {
compatible = "regulator-fixed";
regulator-name = "usbotg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_vbus>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
@ -209,7 +226,7 @@ &ecspi1 {
&gpio2 30 GPIO_ACTIVE_HIGH
&gpio3 19 GPIO_ACTIVE_HIGH
>;
status = "okay";
status = "disabled";
spidev0: spi@0 {
compatible = "spidev";
@ -234,8 +251,22 @@ &fec {
clock-names = "ipg", "ahb", "ptp", "enet_out";
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
phy-handle = <&etnphy>;
phy-supply = <&reg_3v3_etn>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
etnphy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_mdio>;
interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>;
};
};
};
&gpmi {
@ -301,310 +332,318 @@ &iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6qdl-tx6 {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
>;
};
pinctrl_disp0_1: disp0grp-1 {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
/* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_disp0_1: disp0grp-1 {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
/* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_disp0_2: disp0grp-2 {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_disp0_2: disp0grp-2 {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
>;
};
pinctrl_edt_ft5x06: edt-ft5x06grp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
>;
};
pinctrl_edt_ft5x06: edt-ft5x06grp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
>;
};
pinctrl_etnphy_power: etnphy-pwrgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
>;
};
pinctrl_enet_mdio: enet-mdiogrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
>;
};
pinctrl_etnphy_power: etnphy-pwrgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
>;
};
pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
>;
};
pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_lcd0_pwr: lcd0-pwrgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
>;
};
pinctrl_lcd1_pwr: lcd1-pwrgrp {
fsl,pins = <
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
>;
};
pinctrl_lcd0_pwr: lcd0-pwrgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
>;
};
pinctrl_lcd1_pwr: lcd-pwrgrp {
fsl,pins = <
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
>;
};
pinctrl_tsc2007: tsc2007grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_tsc2007: tsc2007grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
>;
};
pinctrl_uart1_rtscts: uart1_rtsctsgrp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart1_rtscts: uart1_rtsctsgrp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
>;
};
pinctrl_uart2_rtscts: uart2_rtsctsgrp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2_rtscts: uart2_rtsctsgrp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
>;
};
pinctrl_uart3_rtscts: uart3_rtsctsgrp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_usbh1_vbus: usbh1-vbusgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
>;
};
pinctrl_uart3_rtscts: uart3_rtsctsgrp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
>;
};
pinctrl_usbh1_vbus: usbh1-vbusgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
>;
};
pinctrl_usbotg_vbus: usbotg-vbusgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
>;
};
pinctrl_usbotg_vbus: usbotg-vbusgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
>;
};
pinctrl_user_led: user-ledgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
>;
};
};
@ -649,19 +688,22 @@ &ssi1 {
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
fsl,uart-has-rtscts;
status = "okay";
};

96
arch/arm/boot/dts/imx6qdl-udoo.dtsi
View File

@ -10,14 +10,49 @@
*/
/ {
aliases {
backlight = &backlight;
panelchan = &panelchan;
panel7 = &panel7;
touchscreenp7 = &touchscreenp7;
};
chosen {
stdout-path = &uart2;
};
backlight: backlight {
compatible = "gpio-backlight";
gpios = <&gpio1 4 0>;
default-on;
status = "disabled";
};
memory {
reg = <0x10000000 0x40000000>;
};
panel7: panel7 {
/*
* in reality it is a -20t (parallel) model,
* but with LVDS bridge chip attached,
* so it is equivalent to -19t model in drive
* characteristics
*/
compatible = "urt,umsh-8596md-19t";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel>;
power-supply = <&reg_panel>;
backlight = <&backlight>;
status = "disabled";
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@ -33,6 +68,14 @@ reg_usb_h1_vbus: regulator@0 {
startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
gpio = <&gpio7 12 0>;
};
reg_panel: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "lcd_panel";
enable-active-high;
gpio = <&gpio1 2 0>;
};
};
sound {
@ -67,6 +110,24 @@ &i2c2 {
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
touchscreenp7: touchscreenp7@55 {
compatible = "sitronix,st1232";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touchscreenp7>;
reg = <0x55>;
interrupt-parent = <&gpio1>;
interrupts = <13 8>;
gpios = <&gpio1 15 0>;
status = "disabled";
};
};
&iomuxc {
imx6q-udoo {
pinctrl_enet: enetgrp {
@ -97,6 +158,27 @@ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1
>;
};
pinctrl_panel: panelgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70
>;
};
pinctrl_touchscreenp7: touchscreenp7grp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
@ -154,6 +236,20 @@ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
};
};
&ldb {
status = "okay";
panelchan: lvds-channel@0 {
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;

59
arch/arm/boot/dts/imx6qp-nitrogen6_max.dts Normal file
View File

@ -0,0 +1,59 @@
/*
* Copyright 2016 Boundary Devices, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6qp.dtsi"
#include "imx6qdl-nitrogen6_max.dtsi"
/ {
model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX Board";
compatible = "boundary,imx6qp-nitrogen6_max", "fsl,imx6qp";
};
&pcie {
status = "disabled";
};
&sata {
status = "okay";
};

709
arch/arm/boot/dts/imx6sx-nitrogen6sx.dts Normal file
View File

@ -0,0 +1,709 @@
/*
* Copyright (C) 2016 Boundary Devices, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6sx.dtsi"
/ {
model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board";
compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx";
aliases {
fb_lcd = &lcdif1;
t_lcd = &t_lcd;
};
memory {
reg = <0x80000000 0x40000000>;
};
backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&reg_3p3v>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_can1_3v3: regulator-can1-3v3 {
compatible = "regulator-fixed";
regulator-name = "can1-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
};
reg_can2_3v3: regulator-can2-3v3 {
compatible = "regulator-fixed";
regulator-name = "can2-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_vbus>;
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_wlan: regulator-wlan {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wlan>;
compatible = "regulator-fixed";
clocks = <&clks IMX6SX_CLK_CKO>;
clock-names = "slow";
regulator-name = "wlan-en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <70000>;
gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx6sx-nitrogen6sx-sgtl5000";
cpu-dai = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <5>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0xc0000>;
read-only;
};
partition@c0000 {
label = "env";
reg = <0xc0000 0x2000>;
read-only;
};
partition@c2000 {
label = "Kernel";
reg = <0xc2000 0x11e000>;
};
partition@1e0000 {
label = "M4";
reg = <0x1e0000 0x20000>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
phy-supply = <&reg_3p3v>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@4 {
reg = <4>;
};
ethphy2: ethernet-phy@5 {
reg = <5>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rgmii";
phy-handle = <&ethphy2>;
phy-supply = <&reg_3p3v>;
fsl,magic-packet;
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can1_3v3>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can2_3v3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sgtl5000>;
reg = <0x0a>;
clocks = <&clks IMX6SX_CLK_CKO2>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_1p8v>;
VDDD-supply = <&reg_1p8v>;
assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>,
<&clks IMX6SX_CLK_CKO2>;
assigned-clock-parents = <&clks IMX6SX_CLK_OSC>;
assigned-clock-rates = <0>, <24000000>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif1>;
lcd-supply = <&reg_3p3v>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&t_lcd>;
t_lcd: t_lcd_default {
clock-frequency = <74160000>;
hactive = <1280>;
vactive = <720>;
hback-porch = <220>;
hfront-porch = <110>;
vback-porch = <20>;
vfront-porch = <5>;
hsync-len = <40>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2>;
dr_mode = "host";
disable-over-current;
reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};
&usdhc3 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <4>;
non-removable;
keep-power-in-suspend;
vmmc-supply = <&reg_wlan>;
cap-power-off-card;
cap-sdio-irq;
status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio7>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
};
wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
interrupt-parent = <&gpio7>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
ref-clock-frequency = <38400000>;
};
};
&usdhc4 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
bus-width = <8>;
non-removable;
vmmc-supply = <&reg_1p8v>;
keep-power-in-suspend;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0
MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0
MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0
MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0
MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0
MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1
MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1
MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1
MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1
MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1
MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1
MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0
MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0
MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0
MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0
MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0
MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0
MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0
MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0
MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0
MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0
MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0
MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0
MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0
MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x000b0
MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0
/* Test points */
MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0
MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_lcdif1: lcdif1grp {
fsl,pins = <
MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0
MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0xb0b0
MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0xb0b0
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0
>;
};
pinctrl_reg_wlan: reg-wlangrp {
fsl,pins = <
MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0
MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0
>;
};
pinctrl_sgtl5000: sgtl5000grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0
MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0
MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0
MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1
MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1
MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0
MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1
>;
};
pinctrl_usbotg1_vbus: usbotg1-vbusgrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0
>;
};
pinctrl_usbotg2: usbotg2grp {
fsl,pins = <
MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071
>;
};
pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp {
fsl,pins = <
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071
MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071
>;
};
pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp {
fsl,pins = <
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
>;
};
pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp {
fsl,pins = <
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
>;
};
};

67
arch/arm/boot/dts/imx6sx-sdb-sai.dts Normal file
View File

@ -0,0 +1,67 @@
/*
* Copyright (C) 2016 NXP Semiconductors
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx6sx-sdb.dts"
/ {
sound {
audio-cpu = <&sai1>;
};
};
&audmux {
/* pin conflict with sai */
status = "disabled";
};
&sai1 {
status = "okay";
};
&sdma {
gpr = <&gpr>;
/* SDMA event remap for SAI1 */
fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
};
&ssi2 {
status = "disabled";
};

16
arch/arm/boot/dts/imx6sx-sdb.dtsi
View File

@ -254,6 +254,12 @@ &snvs_poweroff {
status = "okay";
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
status = "disabled";
};
&ssi2 {
status = "okay";
};
@ -468,6 +474,16 @@ MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0
MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0
MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0
MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1

6
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -970,8 +970,7 @@ sai1: sai@021d4000 {
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&sdma 31 23 0>, <&sdma 32 23 0>;
dma-source = <&gpr 0 15 0 16>;
dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
status = "disabled";
};
@ -990,8 +989,7 @@ sai2: sai@021dc000 {
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&sdma 33 23 0>, <&sdma 34 23 0>;
dma-source = <&gpr 0 17 0 18>;
dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
status = "disabled";
};

53
arch/arm/boot/dts/imx6ul-tx6ul-0010.dts Normal file
View File

@ -0,0 +1,53 @@
/*
* Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6ul.dtsi"
#include "imx6ul-tx6ul.dtsi"
/ {
model = "Ka-Ro electronics TXUL-0010 Module";
compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
aliases {
/delete-property/ mmc1;
};
};

68
arch/arm/boot/dts/imx6ul-tx6ul-0011.dts Normal file
View File

@ -0,0 +1,68 @@
/*
* Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6ul.dtsi"
#include "imx6ul-tx6ul.dtsi"
/ {
model = "Ka-Ro electronics TXUL-0011 Module";
compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
aliases {
mmc0 = &usdhc2;
mmc1 = &usdhc1;
};
};
&gpmi {
status = "disabled";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
no-1-8-v;
non-removable;
fsl,wp-controller;
status = "okay";
};

271
arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts Normal file
View File

@ -0,0 +1,271 @@
/*
* Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6ul.dtsi"
#include "imx6ul-tx6ul.dtsi"
/ {
model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard";
compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
aliases {
lcdif_24bit_pins_a = &pinctrl_disp0_3;
mmc0 = &usdhc1;
/delete-property/ mmc1;
serial2 = &uart3;
serial4 = &uart5;
};
/delete-node/ sound;
};
&can1 {
xceiver-supply = <&reg_3v3>;
};
&can2 {
xceiver-supply = <&reg_3v3>;
};
&ds1339 {
status = "disabled";
};
&fec1 {
pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>;
/delete-node/ mdio;
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
phy-supply = <&reg_3v3_etn>;
phy-handle = <&etnphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
etnphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_etnphy0_int>;
interrupt-parent = <&gpio5>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
interrupts-extended = <&gpio5 5 IRQ_TYPE_EDGE_FALLING>;
status = "okay";
};
etnphy1: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_etnphy1_int>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
interrupts-extended = <&gpio4 27 IRQ_TYPE_EDGE_FALLING>;
status = "okay";
};
};
};
&i2c_gpio {
status = "disabled";
};
&i2c2 {
/delete-node/ codec@0a;
/delete-node/ touchscreen@48;
rtc: mcp7940x@6f {
compatible = "microchip,mcp7940x";
reg = <0x6f>;
};
};
&kpp {
status = "disabled";
};
&lcdif {
pinctrl-0 = <&pinctrl_disp0_3>;
};
&reg_usbotg_vbus{
status = "disabled";
};
&usdhc1 {
pinctrl-0 = <&pinctrl_usdhc1>;
non-removable;
/delete-property/ cd-gpios;
cap-sdio-irq;
};
&uart1 {
pinctrl-0 = <&pinctrl_uart1>;
/delete-property/ fsl,uart-has-rtscts;
};
&uart2 {
pinctrl-0 = <&pinctrl_uart2>;
/delete-property/ fsl,uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&uart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
status = "okay";
};
&uart7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart7>;
status = "okay";
};
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8>;
status = "disabled"; /* conflicts with LCDIF */
};
&iomuxc {
hoggrp {
fsl,pins = <
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x0b0b0 /* WLAN_RESET */
>;
};
pinctrl_disp0_3: disp0grp-3 {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
/* LCD_DATA08..09 not wired */
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
/* LCD_DATA16..17 not wired */
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
>;
};
pinctrl_enet2_mdio: enet2-mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x0b0b0
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0b0b0
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x0b0b0
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x0b0b0
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x0b0b0
MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x0b0b0
>;
};
pinctrl_uart7: uart7grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0b0b0
MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x0b0b0
>;
};
pinctrl_uart8: uart8grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0b0b0
MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x0b0b0
>;
};
};

973
arch/arm/boot/dts/imx6ul-tx6ul.dtsi Normal file
View File

@ -0,0 +1,973 @@
/*
* Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
/ {
aliases {
can0 = &can2;
can1 = &can1;
display = &display;
i2c0 = &i2c2;
i2c1 = &i2c_gpio;
i2c2 = &i2c1;
i2c3 = &i2c3;
i2c4 = &i2c4;
lcdif_23bit_pins_a = &pinctrl_disp0_1;
lcdif_24bit_pins_a = &pinctrl_disp0_2;
pwm0 = &pwm5;
reg_can_xcvr = &reg_can_xcvr;
serial2 = &uart5;
serial4 = &uart3;
spi0 = &ecspi2;
spi1 = &spi_gpio;
stk5led = &user_led;
usbh1 = &usbotg2;
usbotg = &usbotg1;
};
chosen {
stdout-path = &uart1;
};
memory {
reg = <0 0>; /* will be filled by U-Boot */
};
clocks {
mclk: mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
};
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_rst>;
enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
power-supply = <&reg_lcd_pwr>;
/*
* a poor man's way to create a 1:1 relationship between
* the PWM value and the actual duty cycle
*/
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <50>;
};
i2c_gpio: i2c-gpio {
compatible = "i2c-gpio";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c_gpio>;
gpios = <
&gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
&gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
>;
clock-frequency = <400000>;
status = "okay";
ds1339: rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
status = "disabled";
};
};
leds {
compatible = "gpio-leds";
user_led: user {
label = "Heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_3v3_etn: regulator-3v3etn {
compatible = "regulator-fixed";
regulator-name = "3V3_ETN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_etnphy_power>;
gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_2v5: regulator-2v5 {
compatible = "regulator-fixed";
regulator-name = "2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_can_xcvr: regulator-canxcvr {
compatible = "regulator-fixed";
regulator-name = "CAN XCVR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan_xcvr>;
gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
enable-active-low;
};
reg_lcd_pwr: regulator-lcdpwr {
compatible = "regulator-fixed";
regulator-name = "LCD POWER";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_pwr>;
gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
};
reg_usbh1_vbus: regulator-usbh1vbus {
compatible = "regulator-fixed";
regulator-name = "usbh1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg_vbus: regulator-usbotgvbus {
compatible = "regulator-fixed";
regulator-name = "usbotg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
spi_gpio: spi-gpio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi_gpio>;
gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
num-chipselects = <2>;
cs-gpios = <
&gpio1 29 GPIO_ACTIVE_HIGH
&gpio1 10 GPIO_ACTIVE_HIGH
>;
status = "disabled";
spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <660000>;
};
spi@1 {
compatible = "spidev";
reg = <1>;
spi-max-frequency = <660000>;
};
};
sound {
compatible = "karo,imx6ul-tx6ul-sgtl5000",
"simple-audio-card";
simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Line", "Line In",
"Line", "Line Out",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
cpu_dai: simple-audio-card,cpu {
sound-dai = <&sai2>;
};
codec_dai: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
};
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can_xcvr>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can_xcvr>;
status = "okay";
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <
&gpio1 29 GPIO_ACTIVE_HIGH
&gpio1 10 GPIO_ACTIVE_HIGH
>;
status = "disabled";
spidev0: spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <60000000>;
};
spidev1: spi@1 {
compatible = "spidev";
reg = <1>;
spi-max-frequency = <60000000>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
phy-supply = <&reg_3v3_etn>;
phy-handle = <&etnphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
etnphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_etnphy0_int>;
interrupt-parent = <&gpio5>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
status = "okay";
};
etnphy1: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_etnphy1_int>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
status = "okay";
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
phy-supply = <&reg_3v3_etn>;
phy-handle = <&etnphy1>;
status = "disabled";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <400000>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_2v5>;
VDDIO-supply = <&reg_3v3>;
clocks = <&mclk>;
};
polytouch: polytouch@38 {
compatible = "edt,edt-ft5x06";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_edt_ft5x06>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
wakeup-source;
};
touchscreen: touchscreen@48 {
compatible = "ti,tsc2007";
reg = <0x48>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc2007>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_NONE>;
gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
ti,x-plate-ohms = <660>;
wakeup-source;
};
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp>;
/* sample keymap */
/* row/col 0..3 are mapped to KPP row/col 4..7 */
linux,keymap = <
MATRIX_KEY(4, 4, KEY_POWER)
MATRIX_KEY(4, 5, KEY_KP0)
MATRIX_KEY(4, 6, KEY_KP1)
MATRIX_KEY(4, 7, KEY_KP2)
MATRIX_KEY(5, 4, KEY_KP3)
MATRIX_KEY(5, 5, KEY_KP4)
MATRIX_KEY(5, 6, KEY_KP5)
MATRIX_KEY(5, 7, KEY_KP6)
MATRIX_KEY(6, 4, KEY_KP7)
MATRIX_KEY(6, 5, KEY_KP8)
MATRIX_KEY(6, 6, KEY_KP9)
>;
status = "okay";
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp0_1>;
lcd-supply = <&reg_lcd_pwr>;
display = <&display>;
status = "okay";
display: display@di0 {
bits-per-pixel = <32>;
bus-width = <24>;
status = "okay";
display-timings {
VGA {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hsync-len = <96>;
hfront-porch = <16>;
vback-porch = <31>;
vsync-len = <2>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ETV570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
hback-porch = <114>;
hsync-len = <30>;
hfront-porch = <16>;
vback-porch = <32>;
vsync-len = <3>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ET0350 {
clock-frequency = <6413760>;
hactive = <320>;
vactive = <240>;
hback-porch = <34>;
hsync-len = <34>;
hfront-porch = <20>;
vback-porch = <15>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ET0430 {
clock-frequency = <9009000>;
hactive = <480>;
vactive = <272>;
hback-porch = <2>;
hsync-len = <41>;
hfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
vfront-porch = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
ET0500 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ET0700 { /* same as ET0500 */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hsync-len = <128>;
hfront-porch = <40>;
vback-porch = <33>;
vsync-len = <2>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
ETQ570 {
clock-frequency = <6596040>;
hactive = <320>;
vactive = <240>;
hback-porch = <38>;
hsync-len = <30>;
hfront-porch = <30>;
vback-porch = <16>;
vsync-len = <3>;
vfront-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
};
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
#pwm-cells = <3>;
status = "okay";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
fsl,uart-has-rtscts;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usbotg_vbus>;
dr_mode = "peripheral";
disable-over-current;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usbh1_vbus>;
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
bus-width = <4>;
no-1-8-v;
cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
fsl,wp-controller;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */
>;
};
pinctrl_disp0_1: disp0grp-1 {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
/* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
>;
};
pinctrl_disp0_2: disp0grp-2 {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */
MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */
MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */
>;
};
pinctrl_edt_ft5x06: edt-ft5x06grp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1
>;
};
pinctrl_enet1_mdio: enet1-mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>;
};
pinctrl_etnphy_power: etnphy-pwrgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */
>;
};
pinctrl_etnphy0_int: etnphy-intgrp-0 {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */
>;
};
pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */
>;
};
pinctrl_etnphy1_int: etnphy-intgrp-1 {
fsl,pins = <
MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */
>;
};
pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
>;
};
pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>;
};
pinctrl_i2c_gpio: i2c-gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1
MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0
>;
};
pinctrl_lcd_pwr: lcd-pwrgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */
>;
};
pinctrl_lcd_rst: lcd-rstgrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
>;
};
pinctrl_pwm5: pwm5grp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */
>;
};
pinctrl_spi_gpio: spi-gpiogrp {
fsl,pins = <
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */
>;
};
pinctrl_tsc2007: tsc2007grp {
fsl,pins = <
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0
>;
};
pinctrl_uart1_rtscts: uart1-rtsctsgrp {
fsl,pins = <
MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0
MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0
>;
};
pinctrl_uart2_rtscts: uart2-rtsctsgrp {
fsl,pins = <
MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0
MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0
MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0
>;
};
pinctrl_uart5_rtscts: uart5-rtsctsgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0
>;
};
pinctrl_usbh1_oc: usbh1-ocgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */
>;
};
pinctrl_usbh1_vbus: usbh1-vbusgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */
>;
};
pinctrl_usbotg_oc: usbotg-ocgrp {
fsl,pins = <
MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */
>;
};
pinctrl_usbotg_vbus: usbotg-vbusgrp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1
>;
};
pinctrl_usdhc1_cd: usdhc1cdgrp {
fsl,pins = <
MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1
/* eMMC RESET */
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0
>;
};
};

65
arch/arm/boot/dts/ls1021a.dtsi
View File

@ -119,6 +119,20 @@ gic: interrupt-controller@1400000 {
};
msi1: msi-controller@1570e00 {
compatible = "fsl,1s1021a-msi";
reg = <0x0 0x1570e00 0x0 0x8>;
msi-controller;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
};
msi2: msi-controller@1570e08 {
compatible = "fsl,1s1021a-msi";
reg = <0x0 0x1570e08 0x0 0x8>;
msi-controller;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
};
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
@ -245,7 +259,7 @@ dspi0: dspi@2100000 {
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&platform_clk 1>;
spi-num-chipselects = <5>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
@ -258,7 +272,7 @@ dspi1: dspi@2110000 {
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&platform_clk 1>;
spi-num-chipselects = <5>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
@ -332,6 +346,46 @@ uart3: serial@21d0600 {
status = "disabled";
};
gpio0: gpio@2300000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2320000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@2330000 {
compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
@ -443,8 +497,9 @@ dcu: dcu@2ce0000 {
compatible = "fsl,ls1021a-dcu";
reg = <0x0 0x2ce0000 0x0 0x10000>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 0>;
clock-names = "dcu";
clocks = <&platform_clk 0>,
<&platform_clk 0>;
clock-names = "dcu", "pix";
big-endian;
status = "disabled";
};
@ -587,6 +642,7 @@ pcie@3400000 {
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&msi1>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@ -609,6 +665,7 @@ pcie@3500000 {
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&msi2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,

7
arch/arm/boot/dts/vf-colibri.dtsi
View File

@ -40,6 +40,11 @@
*/
/ {
aliases {
ethernet0 = &fec1;
ethernet1 = &fec0;
};
bl: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
@ -125,8 +130,6 @@ &i2c0 {
};
&nfc {
assigned-clocks = <&clks VF610_CLK_NFC>;
assigned-clock-rates = <33000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
status = "okay";

5
arch/arm/boot/dts/vf500-colibri.dtsi
View File

@ -69,6 +69,11 @@ touchscreen: vf50-touchscreen {
};
};
&nfc {
assigned-clocks = <&clks VF610_CLK_NFC>;
assigned-clock-rates = <33000000>;
};
&iomuxc {
vf610-colibri {
pinctrl_touchctrl_idle: touchctrl_idle {

1
arch/arm/boot/dts/vf500.dtsi
View File

@ -81,6 +81,7 @@ pmu@40089000 {
compatible = "arm,cortex-a5-pmu";
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a5_cpu>;
reg = <0x40089000 0x1000>;
};
};

5
arch/arm/boot/dts/vf610-colibri.dtsi
View File

@ -50,3 +50,8 @@ memory {
reg = <0x80000000 0x10000000>;
};
};
&nfc {
assigned-clocks = <&clks VF610_CLK_NFC>;
assigned-clock-rates = <50000000>;
};

734
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts Normal file
View File

@ -0,0 +1,734 @@
/*
* Copyright (C) 2015, 2016 Zodiac Inflight Innovations
*
* Based on an original 'vf610-twr.dts' which is Copyright 2015,
* Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "vf610.dtsi"
/ {
model = "ZII VF610 Development Board, Rev B";
compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x80000000 0x20000000>;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&pinctrl_leds_debug>;
pinctrl-names = "default";
debug {
label = "zii:green:debug1";
gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
mdio-mux {
compatible = "mdio-mux-gpio";
pinctrl-0 = <&pinctrl_mdio_mux>;
pinctrl-names = "default";
gpios = <&gpio0 8 GPIO_ACTIVE_HIGH
&gpio0 9 GPIO_ACTIVE_HIGH
&gpio0 24 GPIO_ACTIVE_HIGH
&gpio0 25 GPIO_ACTIVE_HIGH>;
mdio-parent-bus = <&mdio1>;
#address-cells = <1>;
#size-cells = <0>;
mdio_mux_1: mdio@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio_mux_2: mdio@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio_mux_4: mdio@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio_mux_8: mdio@8 {
reg = <8>;
#address-cells = <1>;
#size-cells = <0>;
};
};
dsa {
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
dsa,ethernet = <&fec1>;
dsa,mii-bus = <&mdio_mux_1>;
/* 6352 - Primary - 7 ports */
switch0: switch@0-0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00 0>;
eeprom-length = <512>;
port@0 {
reg = <0>;
label = "lan0";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
switch0port5: port@5 {
reg = <5>;
label = "dsa";
phy-mode = "rgmii-txid";
link = <&switch1port6
&switch2port9>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@6 {
reg = <6>;
label = "cpu";
fixed-link {
speed = <100>;
full-duplex;
};
};
};
/* 6352 - Secondary - 7 ports */
switch1: switch@0-1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00 1>;
eeprom-length = <512>;
mii-bus = <&mdio_mux_2>;
port@0 {
reg = <0>;
label = "lan3";
};
port@1 {
reg = <1>;
label = "lan4";
};
port@2 {
reg = <2>;
label = "lan5";
};
switch1port5: port@5 {
reg = <5>;
label = "dsa";
link = <&switch2port9>;
phy-mode = "rgmii-txid";
fixed-link {
speed = <1000>;
full-duplex;
};
};
switch1port6: port@6 {
reg = <6>;
label = "dsa";
phy-mode = "rgmii-txid";
link = <&switch0port5>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
/* 6185 - 10 ports */
switch2: switch@0-2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00 2>;
mii-bus = <&mdio_mux_4>;
port@0 {
reg = <0>;
label = "lan6";
};
port@1 {
reg = <1>;
label = "lan7";
};
port@2 {
reg = <2>;
label = "lan8";
};
port@3 {
reg = <3>;
label = "optical3";
fixed-link {
speed = <1000>;
full-duplex;
link-gpios = <&gpio6 2
GPIO_ACTIVE_HIGH>;
};
};
port@4 {
reg = <4>;
label = "optical4";
fixed-link {
speed = <1000>;
full-duplex;
link-gpios = <&gpio6 3
GPIO_ACTIVE_HIGH>;
};
};
switch2port9: port@9 {
reg = <9>;
label = "dsa";
phy-mode = "rgmii-txid";
link = <&switch1port5
&switch0port5>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_mcu";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
usb0_vbus: regulator-usb0-vbus {
compatible = "regulator-fixed";
pinctrl-0 = <&pinctrl_usb_vbus>;
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 6 0>;
};
spi0 {
compatible = "spi-gpio";
pinctrl-0 = <&pinctrl_gpio_spi0>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
&gpio1 8 GPIO_ACTIVE_HIGH>;
num-chipselects = <2>;
m25p128@0 {
compatible = "m25p128", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <1000000>;
};
at93c46d@1 {
compatible = "atmel,at93c46d";
pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
pinctrl-names = "default";
#address-cells = <0>;
#size-cells = <0>;
reg = <1>;
spi-max-frequency = <500000>;
spi-cs-high;
data-size = <16>;
select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
};
};
};
&adc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_ad5>;
vref-supply = <&reg_vcc_3v3_mcu>;
status = "okay";
};
&edma0 {
status = "okay";
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
bus-width = <4>;
status = "okay";
};
&fec0 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec0>;
status = "okay";
};
&fec1 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
fixed-link {
speed = <100>;
full-duplex;
};
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
};
&i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
status = "okay";
gpio5: pca9554@20 {
compatible = "nxp,pca9554";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
gpio6: pca9554@22 {
compatible = "nxp,pca9554";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9554_22>;
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio2>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
};
lm75@48 {
compatible = "national,lm75";
reg = <0x48>;
};
at24c04@50 {
compatible = "atmel,24c04";
reg = <0x50>;
};
at24c04@52 {
compatible = "atmel,24c04";
reg = <0x52>;
};
ds1682@6b {
compatible = "dallas,ds1682";
reg = <0x6b>;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
tca9548@70 {
compatible = "nxp,pca9548";
pinctrl-0 = <&pinctrl_i2c_mux_reset>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
sfp1: at24c04@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
sfp2: at24c04@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
sfp3: at24c04@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
sfp4: at24c04@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbdev0 {
disable-over-current;
vbus-supply = <&usb0_vbus>;
dr_mode = "host";
status = "okay";
};
&usbh1 {
disable-over-current;
status = "okay";
};
&usbmisc0 {
status = "okay";
};
&usbmisc1 {
status = "okay";
};
&usbphy0 {
status = "okay";
};
&usbphy1 {
status = "okay";
};
&iomuxc {
pinctrl_adc0_ad5: adc0ad5grp {
fsl,pins = <
VF610_PAD_PTC30__ADC0_SE5 0x00a1
>;
};
pinctrl_dspi0: dspi0grp {
fsl,pins = <
VF610_PAD_PTB18__DSPI0_CS1 0x1182
VF610_PAD_PTB19__DSPI0_CS0 0x1182
VF610_PAD_PTB20__DSPI0_SIN 0x1181
VF610_PAD_PTB21__DSPI0_SOUT 0x1182
VF610_PAD_PTB22__DSPI0_SCK 0x1182
>;
};
pinctrl_dspi2: dspi2grp {
fsl,pins = <
VF610_PAD_PTD31__DSPI2_CS1 0x1182
VF610_PAD_PTD30__DSPI2_CS0 0x1182
VF610_PAD_PTD29__DSPI2_SIN 0x1181
VF610_PAD_PTD28__DSPI2_SOUT 0x1182
VF610_PAD_PTD27__DSPI2_SCK 0x1182
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
VF610_PAD_PTA7__GPIO_134 0x219d
>;
};
pinctrl_fec0: fec0grp {
fsl,pins = <
VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d2
VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3
VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
VF610_PAD_PTA6__RMII_CLKIN 0x30d1
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
>;
};
pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
fsl,pins = <
VF610_PAD_PTE27__GPIO_132 0x33e2
>;
};
pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
fsl,pins = <
VF610_PAD_PTB22__GPIO_44 0x33e2
VF610_PAD_PTB21__GPIO_43 0x33e2
VF610_PAD_PTB20__GPIO_42 0x33e1
VF610_PAD_PTB19__GPIO_41 0x33e2
VF610_PAD_PTB18__GPIO_40 0x33e2
>;
};
pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
fsl,pins = <
VF610_PAD_PTE14__GPIO_119 0x31c2
>;
};
pinctrl_i2c0: i2c0grp {
fsl,pins = <
VF610_PAD_PTB14__I2C0_SCL 0x37ff
VF610_PAD_PTB15__I2C0_SDA 0x37ff
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
VF610_PAD_PTB16__I2C1_SCL 0x37ff
VF610_PAD_PTB17__I2C1_SDA 0x37ff
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
VF610_PAD_PTA22__I2C2_SCL 0x37ff
VF610_PAD_PTA23__I2C2_SDA 0x37ff
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
VF610_PAD_PTA30__I2C3_SCL 0x37ff
VF610_PAD_PTA31__I2C3_SDA 0x37ff
>;
};
pinctrl_leds_debug: pinctrl-leds-debug {
fsl,pins = <
VF610_PAD_PTD20__GPIO_74 0x31c2
>;
};
pinctrl_mdio_mux: pinctrl-mdio-mux {
fsl,pins = <
VF610_PAD_PTA18__GPIO_8 0x31c2
VF610_PAD_PTA19__GPIO_9 0x31c2
VF610_PAD_PTB2__GPIO_24 0x31c2
VF610_PAD_PTB3__GPIO_25 0x31c2
>;
};
pinctrl_pca9554_22: pinctrl-pca95540-22 {
fsl,pins = <
VF610_PAD_PTB28__GPIO_98 0x219d
>;
};
pinctrl_pwm0: pwm0grp {
fsl,pins = <
VF610_PAD_PTB0__FTM0_CH0 0x1582
VF610_PAD_PTB1__FTM0_CH1 0x1582
VF610_PAD_PTB2__FTM0_CH2 0x1582
VF610_PAD_PTB3__FTM0_CH3 0x1582
>;
};
pinctrl_qspi0: qspi0grp {
fsl,pins = <
VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3
VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff
VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3
VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3
VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3
VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3
>;
};
pinctrl_uart0: uart0grp {
fsl,pins = <
VF610_PAD_PTB10__UART0_TX 0x21a2
VF610_PAD_PTB11__UART0_RX 0x21a1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
VF610_PAD_PTB23__UART1_TX 0x21a2
VF610_PAD_PTB24__UART1_RX 0x21a1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
VF610_PAD_PTD0__UART2_TX 0x21a2
VF610_PAD_PTD1__UART2_RX 0x21a1
>;
};
pinctrl_usb_vbus: pinctrl-usb-vbus {
fsl,pins = <
VF610_PAD_PTA16__GPIO_6 0x31c2
>;
};
pinctrl_usb0_host: usb0-host-grp {
fsl,pins = <
VF610_PAD_PTD6__GPIO_85 0x0062
>;
};
};

2
arch/arm/boot/dts/vfxxx.dtsi
View File

@ -95,6 +95,7 @@ aips0: aips-bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x00070000>;
ranges;
mscm_cpucfg: cpucfg@40001000 {
@ -481,6 +482,7 @@ aips1: aips-bus@40080000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40080000 0x0007f000>;
ranges;
edma1: dma-controller@40098000 {