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clk: tegra: dfll: Monitor code is DEBUG_FS only
The monitor code is used with DEBUG_FS only, so move it into the corresponding #ifdef block to avoid potential compiler warnings. Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -468,56 +468,6 @@ static unsigned long dfll_scale_dvco_rate(int scale_bits,
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return (u64)dvco_rate * (scale_bits + 1) / DFLL_FREQ_REQ_SCALE_MAX;
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return (u64)dvco_rate * (scale_bits + 1) / DFLL_FREQ_REQ_SCALE_MAX;
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}
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}
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/*
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* Monitor control
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*/
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/**
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* dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
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* @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield
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* @ref_rate: DFLL reference clock rate
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*
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* Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles
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* per second. Returns the converted value.
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*/
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static u64 dfll_calc_monitored_rate(u32 monitor_data,
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unsigned long ref_rate)
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{
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return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE);
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}
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/**
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* dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
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* @td: DFLL instance
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*
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* If the DFLL is enabled, return the last rate reported by the DFLL's
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* internal monitoring hardware. This works in both open-loop and
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* closed-loop mode, and takes the output scaler setting into account.
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* Assumes that the monitor was programmed to monitor frequency before
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* the sample period started. If the driver believes that the DFLL is
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* currently uninitialized or disabled, it will return 0, since
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* otherwise the DFLL monitor data register will return the last
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* measured rate from when the DFLL was active.
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*/
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static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
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{
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u32 v, s;
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u64 pre_scaler_rate, post_scaler_rate;
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if (!dfll_is_running(td))
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return 0;
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v = dfll_readl(td, DFLL_MONITOR_DATA);
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v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;
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pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
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s = dfll_readl(td, DFLL_FREQ_REQ);
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s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT;
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post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate);
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return post_scaler_rate;
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}
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/*
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/*
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* DFLL mode switching
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* DFLL mode switching
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*/
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*/
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@ -1096,6 +1046,55 @@ static void dfll_unregister_clk(struct tegra_dfll *td)
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*/
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*/
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#ifdef CONFIG_DEBUG_FS
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#ifdef CONFIG_DEBUG_FS
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/*
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* Monitor control
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*/
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/**
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* dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
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* @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield
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* @ref_rate: DFLL reference clock rate
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*
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* Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles
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* per second. Returns the converted value.
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*/
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static u64 dfll_calc_monitored_rate(u32 monitor_data,
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unsigned long ref_rate)
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{
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return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE);
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}
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/**
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* dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
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* @td: DFLL instance
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*
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* If the DFLL is enabled, return the last rate reported by the DFLL's
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* internal monitoring hardware. This works in both open-loop and
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* closed-loop mode, and takes the output scaler setting into account.
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* Assumes that the monitor was programmed to monitor frequency before
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* the sample period started. If the driver believes that the DFLL is
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* currently uninitialized or disabled, it will return 0, since
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* otherwise the DFLL monitor data register will return the last
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* measured rate from when the DFLL was active.
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*/
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static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
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{
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u32 v, s;
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u64 pre_scaler_rate, post_scaler_rate;
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if (!dfll_is_running(td))
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return 0;
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v = dfll_readl(td, DFLL_MONITOR_DATA);
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v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;
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pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
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s = dfll_readl(td, DFLL_FREQ_REQ);
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s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT;
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post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate);
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return post_scaler_rate;
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}
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static int attr_enable_get(void *data, u64 *val)
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static int attr_enable_get(void *data, u64 *val)
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{
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{
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