mirror of https://gitee.com/openkylin/linux.git
x86, amd: Extend AMD northbridge caching code to support "Link Control" devices
"Link Control" devices (NB function 4) will be used by L3 cache partitioning on family 0x15. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Cc: <andreas.herrmann3@amd.com> LKML-Reference: <1295881543-572552-4-git-send-email-hans.rosenfeld@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -26,6 +26,7 @@ extern void amd_get_nodes(struct bootnode *nodes);
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struct amd_northbridge {
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struct pci_dev *misc;
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struct pci_dev *link;
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};
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struct amd_northbridge_info {
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@ -20,6 +20,11 @@ struct pci_device_id amd_nb_misc_ids[] = {
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};
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EXPORT_SYMBOL(amd_nb_misc_ids);
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static struct pci_device_id amd_nb_link_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_LINK) },
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{}
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};
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const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
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{ 0x00, 0x18, 0x20 },
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{ 0xff, 0x00, 0x20 },
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@ -45,7 +50,7 @@ int amd_cache_northbridges(void)
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{
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int i = 0;
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struct amd_northbridge *nb;
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struct pci_dev *misc;
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struct pci_dev *misc, *link;
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if (amd_nb_num())
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return 0;
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@ -64,10 +69,12 @@ int amd_cache_northbridges(void)
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amd_northbridges.nb = nb;
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amd_northbridges.num = i;
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misc = NULL;
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link = misc = NULL;
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for (i = 0; i != amd_nb_num(); i++) {
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node_to_amd_nb(i)->misc = misc =
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next_northbridge(misc, amd_nb_misc_ids);
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node_to_amd_nb(i)->link = link =
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next_northbridge(link, amd_nb_link_ids);
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}
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/* some CPU families (e.g. family 0x11) do not support GART */
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@ -518,6 +518,7 @@
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#define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303
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#define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304
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#define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603
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#define PCI_DEVICE_ID_AMD_15H_NB_LINK 0x1604
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#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
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#define PCI_DEVICE_ID_AMD_LANCE 0x2000
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#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
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