mirror of https://gitee.com/openkylin/linux.git
cxgb4vf: Adds SRIOV driver changes for T6 adapter
Adds vnic driver register related changes for T6 adapter Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Hariprasad Shenai
David S. Miller
parent
3ccc6cf74d
commit
41fc2e41d3
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@ -524,7 +524,7 @@ static void unmap_rx_buf(struct adapter *adapter, struct sge_fl *fl)
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*/
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static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
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{
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u32 val;
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u32 val = adapter->params.arch.sge_fl_db;
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/* The SGE keeps track of its Producer and Consumer Indices in terms
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* of Egress Queue Units so we can only tell it about integral numbers
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@ -532,11 +532,9 @@ static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
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*/
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if (fl->pend_cred >= FL_PER_EQ_UNIT) {
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if (is_t4(adapter->params.chip))
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val = PIDX_V(fl->pend_cred / FL_PER_EQ_UNIT);
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val |= PIDX_V(fl->pend_cred / FL_PER_EQ_UNIT);
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else
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val = PIDX_T5_V(fl->pend_cred / FL_PER_EQ_UNIT) |
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DBTYPE_F;
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val |= DBPRIO_F;
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val |= PIDX_T5_V(fl->pend_cred / FL_PER_EQ_UNIT);
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/* Make sure all memory writes to the Free List queue are
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* committed before we tell the hardware about them.
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@ -1084,7 +1082,7 @@ static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *tq,
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* Figure out what HW csum a packet wants and return the appropriate control
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* bits.
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*/
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static u64 hwcsum(const struct sk_buff *skb)
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static u64 hwcsum(enum chip_type chip, const struct sk_buff *skb)
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{
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int csum_type;
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const struct iphdr *iph = ip_hdr(skb);
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@ -1116,11 +1114,16 @@ static u64 hwcsum(const struct sk_buff *skb)
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goto nocsum;
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}
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if (likely(csum_type >= TX_CSUM_TCPIP))
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return TXPKT_CSUM_TYPE_V(csum_type) |
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TXPKT_IPHDR_LEN_V(skb_network_header_len(skb)) |
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TXPKT_ETHHDR_LEN_V(skb_network_offset(skb) - ETH_HLEN);
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else {
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if (likely(csum_type >= TX_CSUM_TCPIP)) {
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u64 hdr_len = TXPKT_IPHDR_LEN_V(skb_network_header_len(skb));
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int eth_hdr_len = skb_network_offset(skb) - ETH_HLEN;
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if (chip <= CHELSIO_T5)
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hdr_len |= TXPKT_ETHHDR_LEN_V(eth_hdr_len);
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else
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hdr_len |= T6_TXPKT_ETHHDR_LEN_V(eth_hdr_len);
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return TXPKT_CSUM_TYPE_V(csum_type) | hdr_len;
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} else {
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int start = skb_transport_offset(skb);
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return TXPKT_CSUM_TYPE_V(csum_type) |
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@ -1308,10 +1311,15 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
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* accounting.
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*/
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cpl = (void *)(lso + 1);
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cntrl = (TXPKT_CSUM_TYPE_V(v6 ?
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if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
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cntrl = TXPKT_ETHHDR_LEN_V(eth_xtra_len);
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else
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cntrl = T6_TXPKT_ETHHDR_LEN_V(eth_xtra_len);
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cntrl |= TXPKT_CSUM_TYPE_V(v6 ?
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TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
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TXPKT_IPHDR_LEN_V(l3hdr_len) |
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TXPKT_ETHHDR_LEN_V(eth_xtra_len));
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TXPKT_IPHDR_LEN_V(l3hdr_len);
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txq->tso++;
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txq->tx_cso += ssi->gso_segs;
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} else {
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@ -1328,7 +1336,8 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
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*/
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cpl = (void *)(wr + 1);
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if (skb->ip_summed == CHECKSUM_PARTIAL) {
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cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS_F;
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cntrl = hwcsum(adapter->params.chip, skb) |
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TXPKT_IPCSUM_DIS_F;
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txq->tx_cso++;
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} else
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cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F;
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@ -2247,6 +2256,8 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
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cmd.iqaddr = cpu_to_be64(rspq->phys_addr);
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if (fl) {
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enum chip_type chip =
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CHELSIO_CHIP_VERSION(adapter->params.chip);
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/*
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* Allocate the ring for the hardware free list (with space
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* for its status page) along with the associated software
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@ -2286,7 +2297,9 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
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cmd.fl0dcaen_to_fl0cidxfthresh =
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cpu_to_be16(
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FW_IQ_CMD_FL0FBMIN_V(SGE_FETCHBURSTMIN_64B) |
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FW_IQ_CMD_FL0FBMAX_V(SGE_FETCHBURSTMAX_512B));
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FW_IQ_CMD_FL0FBMAX_V((chip <= CHELSIO_T5) ?
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FETCHBURSTMAX_512B_X :
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FETCHBURSTMAX_256B_X));
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cmd.fl0size = cpu_to_be16(flsz);
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cmd.fl0addr = cpu_to_be64(fl->addr);
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}
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@ -51,6 +51,7 @@
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*/
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#define CHELSIO_T4 0x4
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#define CHELSIO_T5 0x5
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#define CHELSIO_T6 0x6
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enum chip_type {
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T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
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@ -156,6 +157,12 @@ struct vpd_params {
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u32 cclk; /* Core Clock (KHz) */
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};
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/* Stores chip specific parameters */
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struct arch_specific_params {
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u32 sge_fl_db;
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u16 mps_tcam_size;
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};
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/*
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* Global Receive Side Scaling (RSS) parameters in host-native format.
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*/
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@ -215,6 +222,7 @@ struct adapter_params {
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struct vpd_params vpd; /* Vital Product Data */
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struct rss_params rss; /* Receive Side Scaling */
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struct vf_resources vfres; /* Virtual Function Resource limits */
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struct arch_specific_params arch; /* chip specific params */
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enum chip_type chip; /* chip code */
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u8 nports; /* # of Ethernet "ports" */
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};
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@ -1191,9 +1191,7 @@ int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free,
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unsigned nfilters = 0;
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unsigned int rem = naddr;
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struct fw_vi_mac_cmd cmd, rpl;
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unsigned int max_naddr = is_t4(adapter->params.chip) ?
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NUM_MPS_CLS_SRAM_L_INSTANCES :
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NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
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unsigned int max_naddr = adapter->params.arch.mps_tcam_size;
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if (naddr > max_naddr)
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return -EINVAL;
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@ -1285,9 +1283,7 @@ int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
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struct fw_vi_mac_exact *p = &cmd.u.exact[0];
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size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
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u.exact[1]), 16);
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unsigned int max_naddr = is_t4(adapter->params.chip) ?
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NUM_MPS_CLS_SRAM_L_INSTANCES :
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NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
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unsigned int max_mac_addr = adapter->params.arch.mps_tcam_size;
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/*
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* If this is a new allocation, determine whether it should be
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@ -1310,7 +1306,7 @@ int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
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if (ret == 0) {
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p = &rpl.u.exact[0];
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ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
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if (ret >= max_naddr)
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if (ret >= max_mac_addr)
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ret = -ENOMEM;
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}
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return ret;
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@ -1590,11 +1586,25 @@ int t4vf_prep_adapter(struct adapter *adapter)
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switch (CHELSIO_PCI_ID_VER(adapter->pdev->device)) {
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case CHELSIO_T4:
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adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, 0);
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adapter->params.arch.sge_fl_db = DBPRIO_F;
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adapter->params.arch.mps_tcam_size =
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NUM_MPS_CLS_SRAM_L_INSTANCES;
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break;
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case CHELSIO_T5:
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chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
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adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, chipid);
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adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
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adapter->params.arch.mps_tcam_size =
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NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
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break;
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case CHELSIO_T6:
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chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
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adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, chipid);
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adapter->params.arch.sge_fl_db = 0;
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adapter->params.arch.mps_tcam_size =
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NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
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break;
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}
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