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x86: Clean up mtrr/amd.c: 

Fix trivial style problems :

  ERROR: trailing whitespace
  WARNING: line over 80 characters
  ERROR: do not use C99 // comments

arch/x86/kernel/cpu/mtrr/amd.o:

   text	   data	    bss	    dec	    hex	filename
    501	     32	      0	    533	    215	amd.o.before
    501	     32	      0	    533	    215	amd.o.after

md5:
   62f795eb840ee2d17b03df89e789e76c  amd.o.before.asm
   62f795eb840ee2d17b03df89e789e76c  amd.o.after.asm

Suggested-by: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Yinghai Lu <yinghai@kernel.org>
LKML-Reference: <20090703164225.GA21447@elte.hu>
[ Also restructured comments to be standard, removed stray return,
  converted function description to DocBook style, etc. ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Jaswinder Singh Rajput 2009-07-04 07:50:00 +05:30 committed by Ingo Molnar
parent d7e57676e3
commit 42204455f1
1 changed files with 51 additions and 46 deletions
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97
arch/x86/kernel/cpu/mtrr/amd.c
View File

@ -7,15 +7,15 @@
static void static void
amd_get_mtrr(unsigned int reg, unsigned long *base, amd_get_mtrr(unsigned int reg, unsigned long *base,
unsigned long *size, mtrr_type * type) unsigned long *size, mtrr_type *type)
{ {
unsigned long low, high; unsigned long low, high;
rdmsr(MSR_K6_UWCCR, low, high); rdmsr(MSR_K6_UWCCR, low, high);
/* Upper dword is region 1, lower is region 0 */ /* Upper dword is region 1, lower is region 0 */
if (reg == 1) if (reg == 1)
low = high; low = high;
/* The base masks off on the right alignment */ /* The base masks off on the right alignment */
*base = (low & 0xFFFE0000) >> PAGE_SHIFT; *base = (low & 0xFFFE0000) >> PAGE_SHIFT;
*type = 0; *type = 0;
if (low & 1) if (low & 1)
@ -27,74 +27,81 @@ amd_get_mtrr(unsigned int reg, unsigned long *base,
return; return;
} }
/* /*
* This needs a little explaining. The size is stored as an * This needs a little explaining. The size is stored as an
* inverted mask of bits of 128K granularity 15 bits long offset * inverted mask of bits of 128K granularity 15 bits long offset
* 2 bits * 2 bits.
* *
* So to get a size we do invert the mask and add 1 to the lowest * So to get a size we do invert the mask and add 1 to the lowest
* mask bit (4 as its 2 bits in). This gives us a size we then shift * mask bit (4 as its 2 bits in). This gives us a size we then shift
* to turn into 128K blocks * to turn into 128K blocks.
* *
* eg 111 1111 1111 1100 is 512K * eg 111 1111 1111 1100 is 512K
* *
* invert 000 0000 0000 0011 * invert 000 0000 0000 0011
* +1 000 0000 0000 0100 * +1 000 0000 0000 0100
* *128K ... * *128K ...
*/ */
low = (~low) & 0x1FFFC; low = (~low) & 0x1FFFC;
*size = (low + 4) << (15 - PAGE_SHIFT); *size = (low + 4) << (15 - PAGE_SHIFT);
return;
} }
static void amd_set_mtrr(unsigned int reg, unsigned long base, /**
unsigned long size, mtrr_type type) * amd_set_mtrr - Set variable MTRR register on the local CPU.
/* [SUMMARY] Set variable MTRR register on the local CPU. *
<reg> The register to set. * @reg The register to set.
<base> The base address of the region. * @base The base address of the region.
<size> The size of the region. If this is 0 the region is disabled. * @size The size of the region. If this is 0 the region is disabled.
<type> The type of the region. * @type The type of the region.
[RETURNS] Nothing. *
*/ * Returns nothing.
*/
static void
amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
{ {
u32 regs[2]; u32 regs[2];
/* /*
* Low is MTRR0 , High MTRR 1 * Low is MTRR0, High MTRR 1
*/ */
rdmsr(MSR_K6_UWCCR, regs[0], regs[1]); rdmsr(MSR_K6_UWCCR, regs[0], regs[1]);
/* /*
* Blank to disable * Blank to disable
*/ */
if (size == 0) if (size == 0) {
regs[reg] = 0; regs[reg] = 0;
else } else {
/* Set the register to the base, the type (off by one) and an /*
inverted bitmask of the size The size is the only odd * Set the register to the base, the type (off by one) and an
bit. We are fed say 512K We invert this and we get 111 1111 * inverted bitmask of the size The size is the only odd
1111 1011 but if you subtract one and invert you get the * bit. We are fed say 512K We invert this and we get 111 1111
desired 111 1111 1111 1100 mask * 1111 1011 but if you subtract one and invert you get the
* desired 111 1111 1111 1100 mask
But ~(x - 1) == ~x + 1 == -x. Two's complement rocks! */ *
* But ~(x - 1) == ~x + 1 == -x. Two's complement rocks!
*/
regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC) regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC)
| (base << PAGE_SHIFT) | (type + 1); | (base << PAGE_SHIFT) | (type + 1);
}
/* /*
* The writeback rule is quite specific. See the manual. Its * The writeback rule is quite specific. See the manual. Its
* disable local interrupts, write back the cache, set the mtrr * disable local interrupts, write back the cache, set the mtrr
*/ */
wbinvd(); wbinvd();
wrmsr(MSR_K6_UWCCR, regs[0], regs[1]); wrmsr(MSR_K6_UWCCR, regs[0], regs[1]);
} }
static int amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type) static int
amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
{ {
/* Apply the K6 block alignment and size rules /*
In order * Apply the K6 block alignment and size rules
o Uncached or gathering only * In order
o 128K or bigger block * o Uncached or gathering only
o Power of 2 block * o 128K or bigger block
o base suitably aligned to the power * o Power of 2 block
*/ * o base suitably aligned to the power
*/
if (type > MTRR_TYPE_WRCOMB || size < (1 << (17 - PAGE_SHIFT)) if (type > MTRR_TYPE_WRCOMB || size < (1 << (17 - PAGE_SHIFT))
|| (size & ~(size - 1)) - size || (base & (size - 1))) || (size & ~(size - 1)) - size || (base & (size - 1)))
return -EINVAL; return -EINVAL;
@ -115,5 +122,3 @@ int __init amd_init_mtrr(void)
set_mtrr_ops(&amd_mtrr_ops); set_mtrr_ops(&amd_mtrr_ops);
return 0; return 0;
} }
//arch_initcall(amd_mtrr_init);