mirror of https://gitee.com/openkylin/linux.git
perf_counter, x86: rework pmc_amd_save_disable_all() and pmc_amd_restore_all()
MSR reads and writes are expensive. This patch adds checks to avoid its usage where possible. [ Impact: micro-optimization on AMD CPUs ] Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: Paul Mackerras <paulus@samba.org> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1241002046-8832-5-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -334,11 +334,13 @@ static u64 pmc_amd_save_disable_all(void)
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for (idx = 0; idx < nr_counters_generic; idx++) {
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u64 val;
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if (!test_bit(idx, cpuc->active_mask))
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continue;
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rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
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if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) {
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val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
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}
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if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
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continue;
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val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
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}
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return enabled;
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@ -372,13 +374,15 @@ static void pmc_amd_restore_all(u64 ctrl)
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return;
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for (idx = 0; idx < nr_counters_generic; idx++) {
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if (test_bit(idx, cpuc->active_mask)) {
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u64 val;
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u64 val;
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rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
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val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
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}
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if (!test_bit(idx, cpuc->active_mask))
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continue;
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rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
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if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
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continue;
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val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
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}
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}
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