mirror of https://gitee.com/openkylin/linux.git
mrf24j40: use regmap for register access
This patch uses the regmap functions for transceiver register settings where it's possible. This means everything except the hotpaths like receive/transmit handling. Reviewed-by: Stefan Schmidt <stefan@osg.samsung.com> Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
This commit is contained in:
Alexander Aring
Marcel Holtmann
parent
b015679200
commit
42c7148e06
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@ -543,35 +543,6 @@ static int read_long_reg(struct mrf24j40 *devrec, u16 reg, u8 *value)
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return ret;
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}
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static int write_long_reg(struct mrf24j40 *devrec, u16 reg, u8 val)
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{
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int ret;
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u16 cmd;
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struct spi_message msg;
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struct spi_transfer xfer = {
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.len = 3,
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.tx_buf = devrec->buf,
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.rx_buf = devrec->buf,
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};
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spi_message_init(&msg);
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spi_message_add_tail(&xfer, &msg);
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cmd = MRF24J40_WRITELONG(reg);
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mutex_lock(&devrec->buffer_mutex);
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devrec->buf[0] = cmd >> 8 & 0xff;
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devrec->buf[1] = cmd & 0xff;
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devrec->buf[2] = val;
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ret = spi_sync(devrec->spi, &msg);
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if (ret)
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dev_err(printdev(devrec),
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"SPI write Failed for long register 0x%hx\n", reg);
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mutex_unlock(&devrec->buffer_mutex);
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return ret;
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}
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/* This function relies on an undocumented write method. Once a write command
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and address is set, as many bytes of data as desired can be clocked into
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the device. The datasheet only shows setting one byte at a time. */
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@ -755,33 +726,23 @@ static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
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static int mrf24j40_start(struct ieee802154_hw *hw)
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{
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struct mrf24j40 *devrec = hw->priv;
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u8 val;
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int ret;
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dev_dbg(printdev(devrec), "start\n");
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ret = read_short_reg(devrec, REG_INTCON, &val);
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if (ret)
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return ret;
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val &= ~(0x1|0x8); /* Clear TXNIE and RXIE. Enable interrupts */
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write_short_reg(devrec, REG_INTCON, val);
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return 0;
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/* Clear TXNIE and RXIE. Enable interrupts */
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return regmap_update_bits(devrec->regmap_short, REG_INTCON,
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0x01 | 0x08, 0x00);
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}
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static void mrf24j40_stop(struct ieee802154_hw *hw)
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{
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struct mrf24j40 *devrec = hw->priv;
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u8 val;
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int ret;
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dev_dbg(printdev(devrec), "stop\n");
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ret = read_short_reg(devrec, REG_INTCON, &val);
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if (ret)
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return;
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val |= 0x1|0x8; /* Set TXNIE and RXIE. Disable Interrupts */
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write_short_reg(devrec, REG_INTCON, val);
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/* Set TXNIE and RXIE. Disable Interrupts */
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regmap_update_bits(devrec->regmap_short, REG_INTCON, 0x01 | 0x08,
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0x01 | 0x08);
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}
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static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
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@ -798,20 +759,20 @@ static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
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/* Set Channel TODO */
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val = (channel-11) << 4 | 0x03;
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write_long_reg(devrec, REG_RFCON0, val);
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/* RF Reset */
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ret = read_short_reg(devrec, REG_RFCTL, &val);
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ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0, 0xf0, val);
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if (ret)
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return ret;
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val |= 0x04;
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write_short_reg(devrec, REG_RFCTL, val);
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val &= ~0x04;
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write_short_reg(devrec, REG_RFCTL, val);
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udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
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/* RF Reset */
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ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x04);
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if (ret)
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return ret;
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return 0;
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ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x00);
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if (!ret)
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udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
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return ret;
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}
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static int mrf24j40_filter(struct ieee802154_hw *hw,
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@ -829,8 +790,8 @@ static int mrf24j40_filter(struct ieee802154_hw *hw,
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addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
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addrl = le16_to_cpu(filt->short_addr) & 0xff;
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write_short_reg(devrec, REG_SADRH, addrh);
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write_short_reg(devrec, REG_SADRL, addrl);
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regmap_write(devrec->regmap_short, REG_SADRH, addrh);
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regmap_write(devrec->regmap_short, REG_SADRL, addrl);
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dev_dbg(printdev(devrec),
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"Set short addr to %04hx\n", filt->short_addr);
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}
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@ -841,7 +802,8 @@ static int mrf24j40_filter(struct ieee802154_hw *hw,
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memcpy(addr, &filt->ieee_addr, 8);
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for (i = 0; i < 8; i++)
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write_short_reg(devrec, REG_EADR0 + i, addr[i]);
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regmap_write(devrec->regmap_short, REG_EADR0 + i,
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addr[i]);
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#ifdef DEBUG
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pr_debug("Set long addr to: ");
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@ -857,8 +819,8 @@ static int mrf24j40_filter(struct ieee802154_hw *hw,
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panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
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panidl = le16_to_cpu(filt->pan_id) & 0xff;
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write_short_reg(devrec, REG_PANIDH, panidh);
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write_short_reg(devrec, REG_PANIDL, panidl);
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regmap_write(devrec->regmap_short, REG_PANIDH, panidh);
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regmap_write(devrec->regmap_short, REG_PANIDL, panidl);
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dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
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}
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@ -868,14 +830,14 @@ static int mrf24j40_filter(struct ieee802154_hw *hw,
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u8 val;
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int ret;
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ret = read_short_reg(devrec, REG_RXMCR, &val);
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if (filt->pan_coord)
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val = 0x8;
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else
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val = 0x0;
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ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x8,
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val);
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if (ret)
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return ret;
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if (filt->pan_coord)
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val |= 0x8;
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else
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val &= ~0x8;
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write_short_reg(devrec, REG_RXMCR, val);
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/* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
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* REG_ORDER is maintained as default (no beacon/superframe).
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@ -976,80 +938,73 @@ static irqreturn_t mrf24j40_isr(int irq, void *data)
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static int mrf24j40_hw_init(struct mrf24j40 *devrec)
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{
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int ret;
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u8 val;
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/* Initialize the device.
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From datasheet section 3.2: Initialization. */
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ret = write_short_reg(devrec, REG_SOFTRST, 0x07);
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ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07);
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if (ret)
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goto err_ret;
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ret = write_short_reg(devrec, REG_PACON2, 0x98);
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ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98);
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if (ret)
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goto err_ret;
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ret = write_short_reg(devrec, REG_TXSTBL, 0x95);
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ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95);
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if (ret)
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goto err_ret;
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ret = write_long_reg(devrec, REG_RFCON0, 0x03);
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ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03);
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if (ret)
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goto err_ret;
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ret = write_long_reg(devrec, REG_RFCON1, 0x01);
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ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01);
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if (ret)
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goto err_ret;
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ret = write_long_reg(devrec, REG_RFCON2, 0x80);
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ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80);
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if (ret)
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goto err_ret;
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ret = write_long_reg(devrec, REG_RFCON6, 0x90);
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ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90);
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if (ret)
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goto err_ret;
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ret = write_long_reg(devrec, REG_RFCON7, 0x80);
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ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80);
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if (ret)
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goto err_ret;
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ret = write_long_reg(devrec, REG_RFCON8, 0x10);
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ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10);
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if (ret)
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goto err_ret;
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ret = write_long_reg(devrec, REG_SLPCON1, 0x21);
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ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21);
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if (ret)
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goto err_ret;
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ret = write_short_reg(devrec, REG_BBREG2, 0x80);
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ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80);
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if (ret)
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goto err_ret;
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ret = write_short_reg(devrec, REG_CCAEDTH, 0x60);
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ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60);
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if (ret)
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goto err_ret;
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ret = write_short_reg(devrec, REG_BBREG6, 0x40);
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ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40);
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if (ret)
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goto err_ret;
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ret = write_short_reg(devrec, REG_RFCTL, 0x04);
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ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04);
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if (ret)
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goto err_ret;
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ret = write_short_reg(devrec, REG_RFCTL, 0x0);
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ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0);
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if (ret)
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goto err_ret;
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udelay(192);
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/* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
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ret = read_short_reg(devrec, REG_RXMCR, &val);
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if (ret)
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goto err_ret;
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val &= ~0x3; /* Clear RX mode (normal) */
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ret = write_short_reg(devrec, REG_RXMCR, val);
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ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00);
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if (ret)
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goto err_ret;
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@ -1057,22 +1012,20 @@ static int mrf24j40_hw_init(struct mrf24j40 *devrec)
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/* Enable external amplifier.
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* From MRF24J40MC datasheet section 1.3: Operation.
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*/
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read_long_reg(devrec, REG_TESTMODE, &val);
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val |= 0x7; /* Configure GPIO 0-2 to control amplifier */
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write_long_reg(devrec, REG_TESTMODE, val);
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regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07,
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0x07);
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read_short_reg(devrec, REG_TRISGPIO, &val);
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val |= 0x8; /* Set GPIO3 as output. */
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write_short_reg(devrec, REG_TRISGPIO, val);
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/* Set GPIO3 as output. */
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regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08,
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0x08);
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read_short_reg(devrec, REG_GPIO, &val);
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val |= 0x8; /* Set GPIO3 HIGH to enable U5 voltage regulator */
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write_short_reg(devrec, REG_GPIO, val);
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/* Set GPIO3 HIGH to enable U5 voltage regulator */
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regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08);
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/* Reduce TX pwr to meet FCC requirements.
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* From MRF24J40MC datasheet section 3.1.1
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*/
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write_long_reg(devrec, REG_RFCON3, 0x28);
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regmap_write(devrec->regmap_long, REG_RFCON3, 0x28);
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}
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return 0;
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