mirror of https://gitee.com/openkylin/linux.git
thermal: qoriq: Convert driver to use regmap API
Convert driver to use regmap API, drop custom LE/BE IO helpers and simplify bit manipulation using regmap_update_bits(). This also allows us to convert some register initialization to use loops and adds convenient debug access to TMU registers via debugfs. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Tested-by: Lucas Stach <l.stach@pengutronix.de> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Angus Ainslie (Purism) <angus@akkea.ca> Cc: linux-imx@nxp.com Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20191210164153.10463-9-andrew.smirnov@gmail.com
This commit is contained in:
Andrey Smirnov
Daniel Lezcano
parent
01dc58420a
commit
4316237bd6
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@ -9,6 +9,8 @@
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/sizes.h>
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#include <linux/thermal.h>
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#include "thermal_core.h"
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@ -24,85 +26,35 @@
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#define TMU_VER1 0x1
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#define TMU_VER2 0x2
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/*
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* QorIQ TMU Registers
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*/
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struct qoriq_tmu_site_regs {
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u32 tritsr; /* Immediate Temperature Site Register */
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u32 tratsr; /* Average Temperature Site Register */
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u8 res0[0x8];
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};
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#define REGS_TMR 0x000 /* Mode Register */
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#define TMR_DISABLE 0x0
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#define TMR_ME 0x80000000
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#define TMR_ALPF 0x0c000000
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struct qoriq_tmu_regs_v1 {
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u32 tmr; /* Mode Register */
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u32 tsr; /* Status Register */
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u32 tmtmir; /* Temperature measurement interval Register */
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u8 res0[0x14];
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u32 tier; /* Interrupt Enable Register */
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u32 tidr; /* Interrupt Detect Register */
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u32 tiscr; /* Interrupt Site Capture Register */
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u32 ticscr; /* Interrupt Critical Site Capture Register */
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u8 res1[0x10];
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u32 tmhtcrh; /* High Temperature Capture Register */
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u32 tmhtcrl; /* Low Temperature Capture Register */
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u8 res2[0x8];
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u32 tmhtitr; /* High Temperature Immediate Threshold */
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u32 tmhtatr; /* High Temperature Average Threshold */
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u32 tmhtactr; /* High Temperature Average Crit Threshold */
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u8 res3[0x24];
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u32 ttcfgr; /* Temperature Configuration Register */
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u32 tscfgr; /* Sensor Configuration Register */
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u8 res4[0x78];
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struct qoriq_tmu_site_regs site[SITES_MAX];
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u8 res5[0x9f8];
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u32 ipbrr0; /* IP Block Revision Register 0 */
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u32 ipbrr1; /* IP Block Revision Register 1 */
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u8 res6[0x310];
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u32 ttrcr[4]; /* Temperature Range Control Register */
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};
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#define REGS_TMTMIR 0x008 /* Temperature measurement interval Register */
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#define TMTMIR_DEFAULT 0x0000000f
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struct qoriq_tmu_regs_v2 {
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u32 tmr; /* Mode Register */
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u32 tsr; /* Status Register */
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u32 tmsr; /* monitor site register */
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u32 tmtmir; /* Temperature measurement interval Register */
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u8 res0[0x10];
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u32 tier; /* Interrupt Enable Register */
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u32 tidr; /* Interrupt Detect Register */
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u8 res1[0x8];
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u32 tiiscr; /* interrupt immediate site capture register */
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u32 tiascr; /* interrupt average site capture register */
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u32 ticscr; /* Interrupt Critical Site Capture Register */
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u32 res2;
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u32 tmhtcr; /* monitor high temperature capture register */
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u32 tmltcr; /* monitor low temperature capture register */
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u32 tmrtrcr; /* monitor rising temperature rate capture register */
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u32 tmftrcr; /* monitor falling temperature rate capture register */
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u32 tmhtitr; /* High Temperature Immediate Threshold */
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u32 tmhtatr; /* High Temperature Average Threshold */
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u32 tmhtactr; /* High Temperature Average Crit Threshold */
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u32 res3;
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u32 tmltitr; /* monitor low temperature immediate threshold */
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u32 tmltatr; /* monitor low temperature average threshold register */
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u32 tmltactr; /* monitor low temperature average critical threshold */
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u32 res4;
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u32 tmrtrctr; /* monitor rising temperature rate critical threshold */
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u32 tmftrctr; /* monitor falling temperature rate critical threshold*/
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u8 res5[0x8];
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u32 ttcfgr; /* Temperature Configuration Register */
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u32 tscfgr; /* Sensor Configuration Register */
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u8 res6[0x78];
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struct qoriq_tmu_site_regs site[SITES_MAX];
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u8 res7[0x9f8];
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u32 ipbrr0; /* IP Block Revision Register 0 */
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u32 ipbrr1; /* IP Block Revision Register 1 */
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u8 res8[0x300];
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u32 teumr0;
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u32 teumr1;
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u32 teumr2;
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u32 res9;
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u32 ttrcr[4]; /* Temperature Range Control Register */
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};
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#define REGS_V2_TMSR 0x008 /* monitor site register */
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#define REGS_V2_TMTMIR 0x00c /* Temperature measurement interval Register */
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#define REGS_TIER 0x020 /* Interrupt Enable Register */
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#define TIER_DISABLE 0x0
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#define REGS_TTCFGR 0x080 /* Temperature Configuration Register */
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#define REGS_TSCFGR 0x084 /* Sensor Configuration Register */
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#define REGS_TRITSR(n) (0x100 + 16 * (n)) /* Immediate Temperature
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* Site Register
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*/
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#define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n
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* Control Register
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*/
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#define REGS_IPBRR(n) (0xbf8 + 4 * (n)) /* IP Block Revision
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* Register n
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*/
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#define REGS_V2_TEUMR(n) (0xf00 + 4 * (n))
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/*
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* Thermal zone data
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@ -113,10 +65,8 @@ struct qoriq_sensor {
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struct qoriq_tmu_data {
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int ver;
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struct qoriq_tmu_regs_v1 __iomem *regs;
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struct qoriq_tmu_regs_v2 __iomem *regs_v2;
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struct regmap *regmap;
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struct clk *clk;
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bool little_endian;
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struct qoriq_sensor sensor[SITES_MAX];
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};
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@ -125,29 +75,13 @@ static struct qoriq_tmu_data *qoriq_sensor_to_data(struct qoriq_sensor *s)
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return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
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}
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static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr)
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{
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if (p->little_endian)
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iowrite32(val, addr);
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else
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iowrite32be(val, addr);
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}
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static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem *addr)
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{
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if (p->little_endian)
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return ioread32(addr);
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else
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return ioread32be(addr);
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}
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static int tmu_get_temp(void *p, int *temp)
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{
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struct qoriq_sensor *qsensor = p;
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struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
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u32 val;
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val = tmu_read(qdata, &qdata->regs->site[qsensor->id].tritsr);
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regmap_read(qdata->regmap, REGS_TRITSR(qsensor->id), &val);
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*temp = (val & 0xff) * 1000;
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return 0;
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@ -189,12 +123,12 @@ static int qoriq_tmu_register_tmu_zone(struct device *dev,
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/* Enable monitoring */
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if (sites != 0) {
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if (qdata->ver == TMU_VER1) {
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tmu_write(qdata, sites | TMR_ME | TMR_ALPF,
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&qdata->regs->tmr);
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regmap_write(qdata->regmap, REGS_TMR,
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sites | TMR_ME | TMR_ALPF);
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} else {
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tmu_write(qdata, sites, &qdata->regs_v2->tmsr);
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tmu_write(qdata, TMR_ME | TMR_ALPF_V2,
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&qdata->regs_v2->tmr);
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regmap_write(qdata->regmap, REGS_V2_TMSR, sites);
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regmap_write(qdata->regmap, REGS_TMR,
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TMR_ME | TMR_ALPF_V2);
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}
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}
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@ -223,7 +157,7 @@ static int qoriq_tmu_calibration(struct device *dev,
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/* Init temperature range registers */
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for (i = 0; i < len; i++)
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tmu_write(data, range[i], &data->regs->ttrcr[i]);
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regmap_write(data->regmap, REGS_TTRnCR(i), range[i]);
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calibration = of_get_property(np, "fsl,tmu-calibration", &len);
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if (calibration == NULL || len % 8) {
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@ -233,9 +167,9 @@ static int qoriq_tmu_calibration(struct device *dev,
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for (i = 0; i < len; i += 8, calibration += 2) {
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val = of_read_number(calibration, 1);
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tmu_write(data, val, &data->regs->ttcfgr);
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regmap_write(data->regmap, REGS_TTCFGR, val);
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val = of_read_number(calibration + 1, 1);
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tmu_write(data, val, &data->regs->tscfgr);
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regmap_write(data->regmap, REGS_TSCFGR, val);
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}
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return 0;
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@ -244,20 +178,40 @@ static int qoriq_tmu_calibration(struct device *dev,
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static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
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{
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/* Disable interrupt, using polling instead */
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tmu_write(data, TIER_DISABLE, &data->regs->tier);
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regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);
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/* Set update_interval */
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if (data->ver == TMU_VER1) {
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tmu_write(data, TMTMIR_DEFAULT, &data->regs->tmtmir);
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regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
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} else {
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tmu_write(data, TMTMIR_DEFAULT, &data->regs_v2->tmtmir);
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tmu_write(data, TEUMR0_V2, &data->regs_v2->teumr0);
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regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
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regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
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}
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/* Disable monitoring */
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tmu_write(data, TMR_DISABLE, &data->regs->tmr);
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regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
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}
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static const struct regmap_range qoriq_yes_ranges[] = {
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regmap_reg_range(REGS_TMR, REGS_TSCFGR),
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regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)),
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regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
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regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
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/* Read only registers below */
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regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
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};
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static const struct regmap_access_table qoriq_wr_table = {
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.yes_ranges = qoriq_yes_ranges,
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.n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges) - 1,
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};
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static const struct regmap_access_table qoriq_rd_table = {
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.yes_ranges = qoriq_yes_ranges,
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.n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges),
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};
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static int qoriq_tmu_probe(struct platform_device *pdev)
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{
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int ret;
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@ -265,18 +219,37 @@ static int qoriq_tmu_probe(struct platform_device *pdev)
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struct qoriq_tmu_data *data;
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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const bool little_endian = of_property_read_bool(np, "little-endian");
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const enum regmap_endian format_endian =
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little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
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const struct regmap_config regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.rd_table = &qoriq_rd_table,
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.wr_table = &qoriq_wr_table,
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.val_format_endian = format_endian,
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.max_register = SZ_4K,
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};
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void __iomem *base;
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data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
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GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->little_endian = of_property_read_bool(np, "little-endian");
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data->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(data->regs)) {
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base = devm_platform_ioremap_resource(pdev, 0);
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ret = PTR_ERR_OR_ZERO(base);
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if (ret) {
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dev_err(dev, "Failed to get memory region\n");
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return PTR_ERR(data->regs);
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return ret;
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}
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data->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
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ret = PTR_ERR_OR_ZERO(data->regmap);
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if (ret) {
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dev_err(dev, "Failed to init regmap (%d)\n", ret);
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return ret;
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}
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data->clk = devm_clk_get_optional(dev, NULL);
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@ -290,10 +263,12 @@ static int qoriq_tmu_probe(struct platform_device *pdev)
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}
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/* version register offset at: 0xbf8 on both v1 and v2 */
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ver = tmu_read(data, &data->regs->ipbrr0);
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ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
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if (ret) {
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dev_err(&pdev->dev, "Failed to read IP block version\n");
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return ret;
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}
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data->ver = (ver >> 8) & 0xff;
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if (data->ver == TMU_VER2)
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data->regs_v2 = (void __iomem *)data->regs;
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qoriq_tmu_init_device(data); /* TMU initialization */
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@ -323,7 +298,7 @@ static int qoriq_tmu_remove(struct platform_device *pdev)
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struct qoriq_tmu_data *data = platform_get_drvdata(pdev);
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/* Disable monitoring */
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tmu_write(data, TMR_DISABLE, &data->regs->tmr);
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regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
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clk_disable_unprepare(data->clk);
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@ -332,13 +307,12 @@ static int qoriq_tmu_remove(struct platform_device *pdev)
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static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
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{
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u32 tmr;
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struct qoriq_tmu_data *data = dev_get_drvdata(dev);
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int ret;
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/* Disable monitoring */
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tmr = tmu_read(data, &data->regs->tmr);
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tmr &= ~TMR_ME;
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tmu_write(data, tmr, &data->regs->tmr);
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ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
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if (ret)
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return ret;
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clk_disable_unprepare(data->clk);
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@ -347,7 +321,6 @@ static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
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static int __maybe_unused qoriq_tmu_resume(struct device *dev)
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{
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u32 tmr;
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int ret;
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struct qoriq_tmu_data *data = dev_get_drvdata(dev);
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@ -356,11 +329,7 @@ static int __maybe_unused qoriq_tmu_resume(struct device *dev)
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return ret;
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/* Enable monitoring */
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tmr = tmu_read(data, &data->regs->tmr);
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tmr |= TMR_ME;
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tmu_write(data, tmr, &data->regs->tmr);
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return 0;
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return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
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}
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static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
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