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arm64: dts: ti: k3-am65-base-board: Add IPC sub-mailbox nodes for R5Fs
Add the sub-mailbox nodes that are used to communicate between MPU and the two R5F remote processors present in the MCU domain to the AM654 EVM base board. These sub-mailbox nodes utilize the System Mailbox clusters 0 and 1. The interrupts associated with the Mailbox Cluster User interrupt used by the sub-mailbox nodes are also added. The GIC_SPI interrupt to be used is dynamically allocated and managed by the System Firmware through the ti-sci-intr irqchip driver. All the remaining mailbox clusters are currently not used on A53 core, and so are disabled. The sub-mailbox nodes added match the hard-coded mailbox configuration used within the TI RTOS IPC software packages. The Cortex R5F processor sub-system is assumed to be running in Split mode, so a sub-mailbox node is used by each of the R5F cores. Only the sub-mailbox node from cluster 0 is used in case of Lockstep mode. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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@ -280,3 +280,61 @@ &pcie1_rc {
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&pcie1_ep {
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&pcie1_ep {
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status = "disabled";
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status = "disabled";
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};
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};
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&mailbox0_cluster0 {
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interrupts = <164 0>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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&mailbox0_cluster1 {
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interrupts = <165 0>;
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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&mailbox0_cluster2 {
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status = "disabled";
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};
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&mailbox0_cluster3 {
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status = "disabled";
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};
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&mailbox0_cluster4 {
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status = "disabled";
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};
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&mailbox0_cluster5 {
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status = "disabled";
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};
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&mailbox0_cluster6 {
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status = "disabled";
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};
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&mailbox0_cluster7 {
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status = "disabled";
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};
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&mailbox0_cluster8 {
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status = "disabled";
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};
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&mailbox0_cluster9 {
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status = "disabled";
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};
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&mailbox0_cluster10 {
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status = "disabled";
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};
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&mailbox0_cluster11 {
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status = "disabled";
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};
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