mirror of https://gitee.com/openkylin/linux.git
EDAC/altera: Do less intrusive error injection
Improve the Arria10 and Stratix10 error injection routine by reading the data and changing just 1 bit before writing back out. Previous routine would overwrite the first bytes to 0 then change 1 bit but this method is less intrusive. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: James Morse <james.morse@arm.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: linux-edac <linux-edac@vger.kernel.org> Link: https://lkml.kernel.org/r/1553635771-32693-1-git-send-email-thor.thayer@linux.intel.com
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@ -1762,28 +1762,24 @@ static ssize_t altr_edac_a10_device_trig2(struct file *file,
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if (trig_type == ALTR_UE_TRIGGER_CHAR) {
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if (trig_type == ALTR_UE_TRIGGER_CHAR) {
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writel(priv->ue_set_mask, set_addr);
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writel(priv->ue_set_mask, set_addr);
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} else {
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} else {
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/* Setup write of 0 to first 4 bytes */
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/* Setup read/write of 4 bytes */
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writel(0x0, drvdata->base + ECC_BLK_WDATA0_OFST);
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writel(0x0, drvdata->base + ECC_BLK_WDATA1_OFST);
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writel(0x0, drvdata->base + ECC_BLK_WDATA2_OFST);
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writel(0x0, drvdata->base + ECC_BLK_WDATA3_OFST);
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/* Setup write of 4 bytes */
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writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
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writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
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/* Setup Address to 0 */
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/* Setup Address to 0 */
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writel(0x0, drvdata->base + ECC_BLK_ADDRESS_OFST);
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writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
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/* Setup accctrl to write & data override */
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/* Setup accctrl to read & ecc & data override */
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writel(ECC_WRITE_DOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
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writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
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/* Kick it. */
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writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
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/* Setup accctrl to read & ecc override */
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writel(ECC_READ_EOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
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/* Kick it. */
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/* Kick it. */
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writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
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writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
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/* Setup write for single bit change */
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/* Setup write for single bit change */
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writel(0x1, drvdata->base + ECC_BLK_WDATA0_OFST);
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writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
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writel(0x0, drvdata->base + ECC_BLK_WDATA1_OFST);
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drvdata->base + ECC_BLK_WDATA0_OFST);
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writel(0x0, drvdata->base + ECC_BLK_WDATA2_OFST);
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writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
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writel(0x0, drvdata->base + ECC_BLK_WDATA3_OFST);
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drvdata->base + ECC_BLK_WDATA1_OFST);
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writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
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drvdata->base + ECC_BLK_WDATA2_OFST);
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writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
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drvdata->base + ECC_BLK_WDATA3_OFST);
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/* Copy Read ECC to Write ECC */
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/* Copy Read ECC to Write ECC */
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writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
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writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
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drvdata->base + ECC_BLK_WECC0_OFST);
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drvdata->base + ECC_BLK_WECC0_OFST);
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@ -321,7 +321,7 @@ struct altr_sdram_mc_data {
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#define ECC_BLK_STARTACC_OFST 0x7C
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#define ECC_BLK_STARTACC_OFST 0x7C
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#define ECC_XACT_KICK 0x10000
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#define ECC_XACT_KICK 0x10000
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#define ECC_WORD_WRITE 0xF
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#define ECC_WORD_WRITE 0xFF
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#define ECC_WRITE_DOVR 0x101
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#define ECC_WRITE_DOVR 0x101
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#define ECC_WRITE_EDOVR 0x103
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#define ECC_WRITE_EDOVR 0x103
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#define ECC_READ_EOVR 0x2
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#define ECC_READ_EOVR 0x2
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