mirror of https://gitee.com/openkylin/linux.git
linux-can-next-for-4.2-20150506
-----BEGIN PGP SIGNATURE----- iQIcBAABCgAGBQJVSoLGAAoJECte4hHFiupU6h0P/inQp/gltr5gqJ5iCscB5SMc wft/Fy9zIcZtxUSCdVIv1GQD1I4UbS9KLunXb/fXdeGrIKAZ6xP4X7TqherY58V6 8b2MdxNG5cOlcldDq7ti9uMiR/ro4M5IVLnUHLOVZNW+eZ0jcXEIxwgrgeVs8ecq SSQPw3CfQQegYP492Iwq2vcljUpB5iZq4py1JVUQb+yACrPQTq/PBEXQ3ZFcn5nF plRaJgZYHs2cCHBQFW+g4xYmGkx3LlolQ4TVvtOQA1eUsn3v4xw7/KXb0HZEdvRZ oknrgA8hgS2U61UuEEW+9A4R8nwOiuEtlMo8BltyctYlNzlo+zdftSBJXNlewLxu sGSy1Zd4+mmYU5dVc3c+mZnDBQ4Rw7fuGZLIhUwp/hZY+wEiGMbFQ3+dc9kyMlP+ rWhMr3vRihqBi2OrWrf8KraEuRmWwQzThT78PMtFFkKEz3HigFWKy61OUDHSjCsy a31BbaoKTMwZnIrnS30C5WeNUcY+CTxmibh/wVkeGsjI0knKcSgExkNXZp0dj12v sNspIVCs0MbCLDw72PPwjJ8SjDe4j7Mt9j1kSKCU8AaWh6gLMz2xmKvMIaICanJo 2nDBYKxoLGRkJoHKxMW8G4g/6KIAGpQGQ17d6FArGc2GpxmxUUbwQxvQZDSGmnwn W+yTmBO2/89+ogIFOK8E =dcJu -----END PGP SIGNATURE----- Merge tag 'linux-can-next-for-4.2-20150506' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next Marc Kleine-Budde says: ==================== pull-request: can-next 2015-05-06 this is a pull request of a seven patches for net-next/master. Andreas Gröger contributes two patches for the janz-ican3 driver. In the first patch, the documentation for already existing sysfs entries is added, the second patch adds support for another module/firmware variant. A patch by Shawn Landden makes the padding in the struct can_frame explicit. The next 4 patches target the flexcan driver, the first one is by David Jander adding some documentation, the reaming three by me add more documentation and two small code cleanups. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
43996fdd9b
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@ -0,0 +1,8 @@
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What: /sys/bus/pci/drivers/janz-cmodio/.../modulbus_number
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Date: May 2010
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KernelVersion: 2.6.35
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Contact: Ira W. Snyder <ira.snyder@gmail.com>
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Description:
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Value representing the HEX switch S2 of the janz carrier board CMOD-IO or CAN-PCI2
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Read-only: value of the configuration switch (0..15)
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@ -0,0 +1,19 @@
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What: /sys/class/net/<iface>/termination
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Date: May 2010
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KernelVersion: 2.6.35
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Contact: Ira W. Snyder <ira.snyder@gmail.com>
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Description:
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Value representing the can bus termination
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Default: 1 (termination active)
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Reading: get actual termination state
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Writing: set actual termination state (0=no termination, 1=termination active)
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What: /sys/class/net/<iface>/fwinfo
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Date: May 2015
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KernelVersion: 3.19
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Contact: Andreas Gröger <andreas24groeger@gmail.com>
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Description:
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Firmware stamp of ican3 module
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Read-only: 32 byte string identification of the ICAN3 module
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(known values: "JANZ-ICAN3 ICANOS 1.xx", "JANZ-ICAN3 CAL/CANopen 1.xx")
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@ -268,6 +268,9 @@ solution for a couple of reasons:
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struct can_frame {
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canid_t can_id; /* 32 bit CAN_ID + EFF/RTR/ERR flags */
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__u8 can_dlc; /* frame payload length in byte (0 .. 8) */
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__u8 __pad; /* padding */
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__u8 __res0; /* reserved / padding */
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__u8 __res1; /* reserved / padding */
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__u8 data[8] __attribute__((aligned(8)));
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};
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@ -267,6 +267,10 @@ static void cmodio_pci_remove(struct pci_dev *dev)
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static const struct pci_device_id cmodio_pci_ids[] = {
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{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_JANZ, 0x0101 },
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{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_JANZ, 0x0100 },
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{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_JANZ, 0x0201 },
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{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_JANZ, 0x0202 },
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{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_JANZ, 0x0201 },
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{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_JANZ, 0x0202 },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, cmodio_pci_ids);
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@ -93,13 +93,13 @@
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(FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
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/* FLEXCAN control register 2 (CTRL2) bits */
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#define FLEXCAN_CRL2_ECRWRE BIT(29)
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#define FLEXCAN_CRL2_WRMFRZ BIT(28)
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#define FLEXCAN_CRL2_RFFN(x) (((x) & 0x0f) << 24)
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#define FLEXCAN_CRL2_TASD(x) (((x) & 0x1f) << 19)
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#define FLEXCAN_CRL2_MRP BIT(18)
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#define FLEXCAN_CRL2_RRS BIT(17)
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#define FLEXCAN_CRL2_EACEN BIT(16)
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#define FLEXCAN_CTRL2_ECRWRE BIT(29)
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#define FLEXCAN_CTRL2_WRMFRZ BIT(28)
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#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
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#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
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#define FLEXCAN_CTRL2_MRP BIT(18)
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#define FLEXCAN_CTRL2_RRS BIT(17)
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#define FLEXCAN_CTRL2_EACEN BIT(16)
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/* FLEXCAN memory error control register (MECR) bits */
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#define FLEXCAN_MECR_ECRWRDIS BIT(31)
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@ -158,7 +158,6 @@
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FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
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/* FLEXCAN message buffers */
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#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
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#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
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#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
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#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
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@ -184,14 +183,14 @@
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* FLEXCAN hardware feature flags
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*
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* Below is some version info we got:
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* SOC Version IP-Version Glitch- [TR]WRN_INT Memory err
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* Filter? connected? detection
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* MX25 FlexCAN2 03.00.00.00 no no no
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* MX28 FlexCAN2 03.00.04.00 yes yes no
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* MX35 FlexCAN2 03.00.00.00 no no no
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* MX53 FlexCAN2 03.00.00.00 yes no no
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* MX6s FlexCAN3 10.00.12.00 yes yes no
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* VF610 FlexCAN3 ? no yes yes
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* SOC Version IP-Version Glitch- [TR]WRN_INT Memory err RTR re-
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* Filter? connected? detection ception in MB
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* MX25 FlexCAN2 03.00.00.00 no no no no
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* MX28 FlexCAN2 03.00.04.00 yes yes no no
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* MX35 FlexCAN2 03.00.00.00 no no no no
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* MX53 FlexCAN2 03.00.00.00 yes no no no
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* MX6s FlexCAN3 10.00.12.00 yes yes no yes
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* VF610 FlexCAN3 ? no yes yes yes?
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*
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* Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
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*/
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@ -221,7 +220,7 @@ struct flexcan_regs {
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u32 imask1; /* 0x28 */
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u32 iflag2; /* 0x2c */
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u32 iflag1; /* 0x30 */
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u32 crl2; /* 0x34 */
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u32 ctrl2; /* 0x34 */
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u32 esr2; /* 0x38 */
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u32 imeur; /* 0x3c */
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u32 lrfr; /* 0x40 */
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@ -230,6 +229,16 @@ struct flexcan_regs {
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u32 rxfir; /* 0x4c */
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u32 _reserved3[12]; /* 0x50 */
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struct flexcan_mb cantxfg[64]; /* 0x80 */
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/* FIFO-mode:
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* MB
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* 0x080...0x08f 0 RX message buffer
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* 0x090...0x0df 1-5 reserverd
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* 0x0e0...0x0ff 6-7 8 entry ID table
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* (mx25, mx28, mx35, mx53)
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* 0x0e0...0x2df 6-7..37 8..128 entry ID table
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* size conf'ed via ctrl2::RFFN
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* (mx6, vf610)
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*/
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u32 _reserved4[408];
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u32 mecr; /* 0xae0 */
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u32 erriar; /* 0xae4 */
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@ -468,7 +477,7 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
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struct flexcan_regs __iomem *regs = priv->base;
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struct can_frame *cf = (struct can_frame *)skb->data;
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u32 can_id;
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u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
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u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
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if (can_dropped_invalid_skb(dev, skb))
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return NETDEV_TX_OK;
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@ -815,7 +824,7 @@ static int flexcan_chip_start(struct net_device *dev)
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{
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struct flexcan_priv *priv = netdev_priv(dev);
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struct flexcan_regs __iomem *regs = priv->base;
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u32 reg_mcr, reg_ctrl, reg_crl2, reg_mecr;
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u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
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int err, i;
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/* enable module */
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@ -918,9 +927,9 @@ static int flexcan_chip_start(struct net_device *dev)
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* and Correction of Memory Errors" to write to
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* MECR register
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*/
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reg_crl2 = flexcan_read(®s->crl2);
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reg_crl2 |= FLEXCAN_CRL2_ECRWRE;
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flexcan_write(reg_crl2, ®s->crl2);
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reg_ctrl2 = flexcan_read(®s->ctrl2);
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reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
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flexcan_write(reg_ctrl2, ®s->ctrl2);
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reg_mecr = flexcan_read(®s->mecr);
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reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
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@ -40,6 +40,7 @@
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#define MSYNC_PEER 0x00 /* ICAN only */
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#define MSYNC_LOCL 0x01 /* host only */
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#define TARGET_RUNNING 0x02
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#define FIRMWARE_STAMP 0x60 /* big endian firmware stamp */
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#define MSYNC_RB0 0x01
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#define MSYNC_RB1 0x02
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@ -83,6 +84,7 @@
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#define MSG_COFFREQ 0x42
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#define MSG_CONREQ 0x43
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#define MSG_CCONFREQ 0x47
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#define MSG_LMTS 0xb4
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/*
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* Janz ICAN3 CAN Inquiry Message Types
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@ -165,6 +167,12 @@
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/* SJA1000 Clock Input */
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#define ICAN3_CAN_CLOCK 8000000
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/* Janz ICAN3 firmware types */
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enum ican3_fwtype {
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ICAN3_FWTYPE_ICANOS,
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ICAN3_FWTYPE_CAL_CANOPEN,
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};
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/* Driver Name */
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#define DRV_NAME "janz-ican3"
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@ -215,6 +223,10 @@ struct ican3_dev {
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struct completion buserror_comp;
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struct can_berr_counter bec;
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/* firmware type */
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enum ican3_fwtype fwtype;
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char fwinfo[32];
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/* old and new style host interface */
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unsigned int iftype;
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@ -750,13 +762,61 @@ static int ican3_set_id_filter(struct ican3_dev *mod, bool accept)
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*/
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static int ican3_set_bus_state(struct ican3_dev *mod, bool on)
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{
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struct can_bittiming *bt = &mod->can.bittiming;
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struct ican3_msg msg;
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u8 btr0, btr1;
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int res;
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memset(&msg, 0, sizeof(msg));
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msg.spec = on ? MSG_CONREQ : MSG_COFFREQ;
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msg.len = cpu_to_le16(0);
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/* This algorithm was stolen from drivers/net/can/sja1000/sja1000.c */
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/* The bittiming register command for the ICAN3 just sets the bit timing */
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/* registers on the SJA1000 chip directly */
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btr0 = ((bt->brp - 1) & 0x3f) | (((bt->sjw - 1) & 0x3) << 6);
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btr1 = ((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) |
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(((bt->phase_seg2 - 1) & 0x7) << 4);
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if (mod->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
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btr1 |= 0x80;
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return ican3_send_msg(mod, &msg);
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if (mod->fwtype == ICAN3_FWTYPE_ICANOS) {
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if (on) {
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/* set bittiming */
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memset(&msg, 0, sizeof(msg));
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msg.spec = MSG_CBTRREQ;
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msg.len = cpu_to_le16(4);
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msg.data[0] = 0x00;
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msg.data[1] = 0x00;
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msg.data[2] = btr0;
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msg.data[3] = btr1;
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res = ican3_send_msg(mod, &msg);
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if (res)
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return res;
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}
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/* can-on/off request */
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memset(&msg, 0, sizeof(msg));
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msg.spec = on ? MSG_CONREQ : MSG_COFFREQ;
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msg.len = cpu_to_le16(0);
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return ican3_send_msg(mod, &msg);
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} else if (mod->fwtype == ICAN3_FWTYPE_CAL_CANOPEN) {
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memset(&msg, 0, sizeof(msg));
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msg.spec = MSG_LMTS;
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if (on) {
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msg.len = cpu_to_le16(4);
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msg.data[0] = 0;
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msg.data[1] = 0;
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msg.data[2] = btr0;
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msg.data[3] = btr1;
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} else {
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msg.len = cpu_to_le16(2);
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msg.data[0] = 1;
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msg.data[1] = 0;
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}
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return ican3_send_msg(mod, &msg);
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}
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return -ENOTSUPP;
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}
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static int ican3_set_termination(struct ican3_dev *mod, bool on)
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@ -1402,7 +1462,7 @@ static int ican3_reset_module(struct ican3_dev *mod)
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return 0;
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msleep(10);
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} while (time_before(jiffies, start + HZ / 4));
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} while (time_before(jiffies, start + HZ / 2));
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netdev_err(mod->ndev, "failed to reset CAN module\n");
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return -ETIMEDOUT;
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@ -1427,6 +1487,17 @@ static int ican3_startup_module(struct ican3_dev *mod)
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return ret;
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}
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/* detect firmware */
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memcpy_fromio(mod->fwinfo, mod->dpm + FIRMWARE_STAMP, sizeof(mod->fwinfo) - 1);
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if (strncmp(mod->fwinfo, "JANZ-ICAN3", 10)) {
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netdev_err(mod->ndev, "ICAN3 not detected (found %s)\n", mod->fwinfo);
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return -ENODEV;
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}
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if (strstr(mod->fwinfo, "CAL/CANopen"))
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mod->fwtype = ICAN3_FWTYPE_CAL_CANOPEN;
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else
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mod->fwtype = ICAN3_FWTYPE_ICANOS;
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/* re-enable interrupts so we can send messages */
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iowrite8(1 << mod->num, &mod->ctrl->int_enable);
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@ -1615,36 +1686,6 @@ static const struct can_bittiming_const ican3_bittiming_const = {
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.brp_inc = 1,
|
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};
|
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|
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/*
|
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* This routine was stolen from drivers/net/can/sja1000/sja1000.c
|
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*
|
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* The bittiming register command for the ICAN3 just sets the bit timing
|
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* registers on the SJA1000 chip directly
|
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*/
|
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static int ican3_set_bittiming(struct net_device *ndev)
|
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{
|
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struct ican3_dev *mod = netdev_priv(ndev);
|
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struct can_bittiming *bt = &mod->can.bittiming;
|
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struct ican3_msg msg;
|
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u8 btr0, btr1;
|
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|
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btr0 = ((bt->brp - 1) & 0x3f) | (((bt->sjw - 1) & 0x3) << 6);
|
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btr1 = ((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) |
|
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(((bt->phase_seg2 - 1) & 0x7) << 4);
|
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if (mod->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
|
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btr1 |= 0x80;
|
||||
|
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memset(&msg, 0, sizeof(msg));
|
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msg.spec = MSG_CBTRREQ;
|
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msg.len = cpu_to_le16(4);
|
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msg.data[0] = 0x00;
|
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msg.data[1] = 0x00;
|
||||
msg.data[2] = btr0;
|
||||
msg.data[3] = btr1;
|
||||
|
||||
return ican3_send_msg(mod, &msg);
|
||||
}
|
||||
|
||||
static int ican3_set_mode(struct net_device *ndev, enum can_mode mode)
|
||||
{
|
||||
struct ican3_dev *mod = netdev_priv(ndev);
|
||||
|
|
@ -1730,11 +1771,22 @@ static ssize_t ican3_sysfs_set_term(struct device *dev,
|
|||
return count;
|
||||
}
|
||||
|
||||
static ssize_t ican3_sysfs_show_fwinfo(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct ican3_dev *mod = netdev_priv(to_net_dev(dev));
|
||||
|
||||
return scnprintf(buf, PAGE_SIZE, "%s\n", mod->fwinfo);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(termination, S_IWUSR | S_IRUGO, ican3_sysfs_show_term,
|
||||
ican3_sysfs_set_term);
|
||||
static DEVICE_ATTR(fwinfo, S_IRUSR | S_IRUGO, ican3_sysfs_show_fwinfo, NULL);
|
||||
|
||||
static struct attribute *ican3_sysfs_attrs[] = {
|
||||
&dev_attr_termination.attr,
|
||||
&dev_attr_fwinfo.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
@ -1794,7 +1846,6 @@ static int ican3_probe(struct platform_device *pdev)
|
|||
|
||||
mod->can.clock.freq = ICAN3_CAN_CLOCK;
|
||||
mod->can.bittiming_const = &ican3_bittiming_const;
|
||||
mod->can.do_set_bittiming = ican3_set_bittiming;
|
||||
mod->can.do_set_mode = ican3_set_mode;
|
||||
mod->can.do_get_berr_counter = ican3_get_berr_counter;
|
||||
mod->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES
|
||||
|
|
@ -1866,7 +1917,7 @@ static int ican3_probe(struct platform_device *pdev)
|
|||
goto out_free_irq;
|
||||
}
|
||||
|
||||
dev_info(dev, "module %d: registered CAN device\n", pdata->modno);
|
||||
netdev_info(mod->ndev, "module %d: registered CAN device\n", pdata->modno);
|
||||
return 0;
|
||||
|
||||
out_free_irq:
|
||||
|
|
|
|||
|
|
@ -95,11 +95,17 @@ typedef __u32 can_err_mask_t;
|
|||
* @can_dlc: frame payload length in byte (0 .. 8) aka data length code
|
||||
* N.B. the DLC field from ISO 11898-1 Chapter 8.4.2.3 has a 1:1
|
||||
* mapping of the 'data length code' to the real payload length
|
||||
* @__pad: padding
|
||||
* @__res0: reserved / padding
|
||||
* @__res1: reserved / padding
|
||||
* @data: CAN frame payload (up to 8 byte)
|
||||
*/
|
||||
struct can_frame {
|
||||
canid_t can_id; /* 32 bit CAN_ID + EFF/RTR/ERR flags */
|
||||
__u8 can_dlc; /* frame payload length in byte (0 .. CAN_MAX_DLEN) */
|
||||
__u8 __pad; /* padding */
|
||||
__u8 __res0; /* reserved / padding */
|
||||
__u8 __res1; /* reserved / padding */
|
||||
__u8 data[CAN_MAX_DLEN] __attribute__((aligned(8)));
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue