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KVM: arm64: Clarify access behaviour for out-of-range SVE register slice IDs 

The existing documentation for which SVE register slice IDs are
considered out-of-range, and what happens when userspace tries to
access them, is cryptic.

This patch rewords the text with the aim of making it a bit easier to
understand.

No functional change.

Suggested-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Dave Martin 2019-04-12 13:25:38 +01:00 committed by Marc Zyngier
parent fe365b4ea6
commit 43b8e1f089
1 changed files with 3 additions and 2 deletions
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5
Documentation/virtual/kvm/api.txt
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@ -2159,8 +2159,9 @@ arm64 SVE registers have the following bit patterns:
0x6050 0000 0015 060 <slice:5> FFR bits[256*slice + 255 : 256*slice]
0x6060 0000 0015 ffff KVM_REG_ARM64_SVE_VLS pseudo-register
Access to slices beyond the maximum vector length configured for the
vcpu (i.e., where 16 * slice >= max_vq (**)) will fail with ENOENT.
Access to register IDs where 2048 * slice >= 128 * max_vq will fail with
ENOENT. max_vq is the vcpu's maximum supported vector length in 128-bit
quadwords: see (**) below.
These registers are only accessible on vcpus for which SVE is enabled.
See KVM_ARM_VCPU_INIT for details.