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drm/i915/icl: Fix MG_DP_MODE() register programming 

Fix the order of lane, port parameters passed to the register macro.

Note that this was already partly fixed by commit
37fc7845df ("drm/i915: Call MG_DP_MODE() macro with the right parameters order")

While at it simplify things by using the macro directly instead of an
unnecessary redirection via an array.

v2:
- Add a note the commit message about simplifying things. (José)

Fixes: 58106b7d81 ("drm/i915: Make MG PHY macros semantically consistent")
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190419071026.32370-1-imre.deak@intel.com
(cherry picked from commit 9c11b12184)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
Imre Deak 2019-04-19 10:10:26 +03:00 committed by Joonas Lahtinen
parent 929eec99f5
commit 447811a686
1 changed files with 8 additions and 10 deletions
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18
drivers/gpu/drm/i915/intel_ddi.c
View File

@ -2905,21 +2905,20 @@ static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum port port = dig_port->base.port; enum port port = dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(dev_priv, port); enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) };
u32 val; u32 val;
int i; int ln;
if (tc_port == PORT_TC_NONE) if (tc_port == PORT_TC_NONE)
return; return;
for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { for (ln = 0; ln < 2; ln++) {
val = I915_READ(mg_regs[i]); val = I915_READ(MG_DP_MODE(ln, port));
val |= MG_DP_MODE_CFG_TR2PWR_GATING | val |= MG_DP_MODE_CFG_TR2PWR_GATING |
MG_DP_MODE_CFG_TRPWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING |
MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_CLNPWR_GATING |
MG_DP_MODE_CFG_DIGPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING |
MG_DP_MODE_CFG_GAONPWR_GATING; MG_DP_MODE_CFG_GAONPWR_GATING;
I915_WRITE(mg_regs[i], val); I915_WRITE(MG_DP_MODE(ln, port), val);
} }
val = I915_READ(MG_MISC_SUS0(tc_port)); val = I915_READ(MG_MISC_SUS0(tc_port));
@ -2938,21 +2937,20 @@ static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum port port = dig_port->base.port; enum port port = dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(dev_priv, port); enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
u32 val; u32 val;
int i; int ln;
if (tc_port == PORT_TC_NONE) if (tc_port == PORT_TC_NONE)
return; return;
for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { for (ln = 0; ln < 2; ln++) {
val = I915_READ(mg_regs[i]); val = I915_READ(MG_DP_MODE(ln, port));
val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING | val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
MG_DP_MODE_CFG_TRPWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING |
MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_CLNPWR_GATING |
MG_DP_MODE_CFG_DIGPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING |
MG_DP_MODE_CFG_GAONPWR_GATING); MG_DP_MODE_CFG_GAONPWR_GATING);
I915_WRITE(mg_regs[i], val); I915_WRITE(MG_DP_MODE(ln, port), val);
} }
val = I915_READ(MG_MISC_SUS0(tc_port)); val = I915_READ(MG_MISC_SUS0(tc_port));