mirror of https://gitee.com/openkylin/linux.git
net: stmmac: fix LPI transitioning for dwmac4
The LPI transitioning logic in stmmac_main uses priv->tx_path_in_lpi_mode to enter/exit LPI. However, priv->tx_path_in_lpi_mode is assigned using the return value from host_irq_status(). So for dwmac4, priv->tx_path_in_lpi_mode was always false, so stmmac_tx_clean() would always try to put us in eee mode, and stmmac_xmit() would never take us out of eee mode. To fix this, make host_irq_status() read and return the LPI irq status also for dwmac4. This also increments the existing LPI counters, so that ethtool --statistics shows LPI transitions also for dwmac4. For dwmac1000, irqs are enabled/disabled using the register named "Interrupt Mask Register", and thus setting a bit disables that specific irq. For dwmac4 the matching register is named "MAC_Interrupt_Enable", and thus setting a bit enables that specific irq. Looking at dwmac1000_core.c, the irqs that are always enabled are: LPI and PMT. Looking at dwmac4_core.c, the irqs that are always enabled are: PMT. To be able to read the LPI irq status, we need to enable the LPI irq also for dwmac4. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -98,7 +98,7 @@
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#define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \
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GMAC_INT_PCS_ANE)
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#define GMAC_INT_DEFAULT_MASK GMAC_INT_PMT_EN
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#define GMAC_INT_DEFAULT_MASK (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN)
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enum dwmac4_irq_status {
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time_stamp_irq = 0x00001000,
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@ -106,6 +106,7 @@ enum dwmac4_irq_status {
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mmc_tx_irq = 0x00000400,
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mmc_rx_irq = 0x00000200,
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mmc_irq = 0x00000100,
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lpi_irq = 0x00000020,
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pmt_irq = 0x00000010,
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};
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@ -132,6 +133,10 @@ enum power_event {
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#define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
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#define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */
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#define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
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#define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
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#define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */
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#define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
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#define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
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/* MAC Debug bitmap */
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#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
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@ -580,6 +580,25 @@ static int dwmac4_irq_status(struct mac_device_info *hw,
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x->irq_receive_pmt_irq_n++;
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}
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/* MAC tx/rx EEE LPI entry/exit interrupts */
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if (intr_status & lpi_irq) {
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/* Clear LPI interrupt by reading MAC_LPI_Control_Status */
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u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
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if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
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ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
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x->irq_tx_path_in_lpi_mode_n++;
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}
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if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
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ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
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x->irq_tx_path_exit_lpi_mode_n++;
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}
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if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
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x->irq_rx_path_in_lpi_mode_n++;
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if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
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x->irq_rx_path_exit_lpi_mode_n++;
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}
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dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
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if (intr_status & PCS_RGSMIIIS_IRQ)
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dwmac4_phystatus(ioaddr, x);
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