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ARM: SoC fixes for 4.4-rc 

This is the final small set of ARM SoC bug fixes for linux-4.4,
 almost all regressions:
 
 OMAP:		data corruption on the Nokia N900 flash
 Allwinner:	Two defconfig change to get USB working again
 ARM Versatile:	Interrupt numbers gone bad after an older bug fix
 Nomadik:	Crashes from incorrect L2 cache settings
 VIA vt8500:	SD/MMC support on WM8650 never worked
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
 "This is the final small set of ARM SoC bug fixes for linux-4.4, almost
  all regressions:

  OMAP:
   - data corruption on the Nokia N900 flash

  Allwinner:
   - Two defconfig change to get USB working again

  ARM Versatile:
   - Interrupt numbers gone bad after an older bug fix

  Nomadik:
   - Crashes from incorrect L2 cache settings

  VIA vt8500:
   - SD/MMC support on WM8650 never worked"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  dts: vt8500: Add SDHC node to DTS file for WM8650
  ARM: Fix broken USB support in multi_v7_defconfig for sunxi devices
  ARM: versatile: fix MMC/SD interrupt assignment
  ARM: nomadik: set latencies to 8 cycles
  ARM: OMAP2+: Fix onenand rate detection to avoid filesystem corruption
  ARM: Fix broken USB support in sunxi_defconfig
This commit is contained in:
Linus Torvalds 2016-01-08 16:11:05 -08:00
parent 516c50cde6 841bcd2e50
commit 44d8a7d5c1
7 changed files with 49 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
View File

@ -25,9 +25,9 @@ L2: l2-cache {
cache-sets = <512>;
cache-line-size = <32>;
/* At full speed latency must be >=2 */
arm,tag-latency = <2>;
arm,data-latency = <2 2>;
arm,dirty-latency = <2>;
arm,tag-latency = <8>;
arm,data-latency = <8 8>;
arm,dirty-latency = <8>;
};
mtu0: mtu@101e2000 {

10
arch/arm/boot/dts/versatile-ab.dts
View File

@ -110,7 +110,11 @@ sic: intc@10003000 {
interrupt-parent = <&vic>;
interrupts = <31>; /* Cascaded to vic */
clear-mask = <0xffffffff>;
valid-mask = <0xffc203f8>;
/*
* Valid interrupt lines mask according to
* table 4-36 page 4-50 of ARM DUI 0225D
*/
valid-mask = <0x0760031b>;
};
dma@10130000 {
@ -266,8 +270,8 @@ aaci@4000 {
};
mmc@5000 {
compatible = "arm,pl180", "arm,primecell";
reg = < 0x5000 0x1000>;
interrupts-extended = <&vic 22 &sic 2>;
reg = <0x5000 0x1000>;
interrupts-extended = <&vic 22 &sic 1>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "mclk", "apb_pclk";
};

20
arch/arm/boot/dts/versatile-pb.dts
View File

@ -5,6 +5,16 @@ / {
compatible = "arm,versatile-pb";
amba {
/* The Versatile PB is using more SIC IRQ lines than the AB */
sic: intc@10003000 {
clear-mask = <0xffffffff>;
/*
* Valid interrupt lines mask according to
* figure 3-30 page 3-74 of ARM DUI 0224B
*/
valid-mask = <0x7fe003ff>;
};
gpio2: gpio@101e6000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x101e6000 0x1000>;
@ -67,6 +77,13 @@ pci-controller@10001000 {
};
fpga {
mmc@5000 {
/*
* Overrides the interrupt assignment from
* the Versatile AB board file.
*/
interrupts-extended = <&sic 22 &sic 23>;
};
uart@9000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x9000 0x1000>;
@ -86,7 +103,8 @@ sci@a000 {
mmc@b000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0xb000 0x1000>;
interrupts-extended = <&vic 23 &sic 2>;
interrupt-parent = <&sic>;
interrupts = <1>, <2>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "mclk", "apb_pclk";
};

9
arch/arm/boot/dts/wm8650.dtsi
View File

@ -187,6 +187,15 @@ uhci@d8007b00 {
interrupts = <43>;
};
sdhc@d800a000 {
compatible = "wm,wm8505-sdhc";
reg = <0xd800a000 0x400>;
interrupts = <20>, <21>;
clocks = <&clksdhc>;
bus-width = <4>;
sdon-inverted;
};
fb: fb@d8050800 {
compatible = "wm,wm8505-fb";
reg = <0xd8050800 0x200>;

1
arch/arm/configs/multi_v7_defconfig
View File

@ -366,6 +366,7 @@ CONFIG_BATTERY_MAX17042=m
CONFIG_CHARGER_MAX14577=m
CONFIG_CHARGER_MAX77693=m
CONFIG_CHARGER_TPS65090=y
CONFIG_AXP20X_POWER=m
CONFIG_POWER_RESET_AS3722=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y

1
arch/arm/configs/sunxi_defconfig
View File

@ -84,6 +84,7 @@ CONFIG_SPI_SUN4I=y
CONFIG_SPI_SUN6I=y
CONFIG_GPIO_SYSFS=y
CONFIG_POWER_SUPPLY=y
CONFIG_AXP20X_POWER=y
CONFIG_THERMAL=y
CONFIG_CPU_THERMAL=y
CONFIG_WATCHDOG=y

14
arch/arm/mach-omap2/gpmc-onenand.c
View File

@ -149,8 +149,8 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
freq = 104;
break;
default:
freq = 54;
break;
pr_err("onenand rate not detected, bad GPMC async timings?\n");
freq = 0;
}
return freq;
@ -271,6 +271,11 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
struct gpmc_timings t;
int ret;
/*
* Note that we need to keep sync_write set for the call to
* omap2_onenand_set_async_mode() to work to detect the onenand
* supported clock rate for the sync timings.
*/
if (gpmc_onenand_data->of_node) {
gpmc_read_settings_dt(gpmc_onenand_data->of_node,
&onenand_async);
@ -281,12 +286,9 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
else
gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
onenand_async.sync_read = false;
onenand_async.sync_write = false;
}
}
omap2_onenand_set_async_mode(onenand_base);
omap2_onenand_calc_async_timings(&t);
ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
@ -310,6 +312,8 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
if (!freq) {
/* Very first call freq is not known */
freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
if (!freq)
return -ENODEV;
set_onenand_cfg(onenand_base);
}