mirror of https://gitee.com/openkylin/linux.git
staging: mfd: add a PMIC driver for HiSilicon 6421 SPMI version
Add the PMIC SPMI driver for the HiSilicon 6421v600. [mchehab+huawei@kernel.org: keep just the MFD driver on this patch, and renamed filenames to better match other upstream drivers] The compete patch is at: https://github.com/96boards-hikey/linux/commit/08464419fba2 Signed-off-by: Mayulong <mayulong1@huawei.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/4ffb2694244baa47387e39e2c5d71243242c1fc1.1597647359.git.mchehab+huawei@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mayulong
Greg Kroah-Hartman
parent
7f3ac6c502
commit
4524ac56cd
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@ -0,0 +1,759 @@
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/*
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* Device driver for regulators in HISI PMIC IC
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*
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* Copyright (c) 2013 Linaro Ltd.
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* Copyright (c) 2011 Hisilicon.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/of_irq.h>
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#include <linux/mfd/hisi_pmic.h>
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#include <linux/irq.h>
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#include <linux/spmi.h>
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#ifndef NO_IRQ
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#define NO_IRQ 0
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#endif
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/* 8-bit register offset in PMIC */
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#define HISI_MASK_STATE 0xff
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#define HISI_IRQ_KEY_NUM 0
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#define HISI_IRQ_KEY_VALUE 0xc0
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#define HISI_IRQ_KEY_DOWN 7
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#define HISI_IRQ_KEY_UP 6
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/*#define HISI_NR_IRQ 25*/
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#define HISI_MASK_FIELD 0xFF
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#define HISI_BITS 8
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#define PMIC_FPGA_FLAG 1
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/*define the first group interrupt register number*/
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#define HISI_PMIC_FIRST_GROUP_INT_NUM 2
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static struct bit_info g_pmic_vbus = {0};
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#ifndef BIT
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#define BIT(x) (0x1U << (x))
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#endif
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static struct hisi_pmic *g_pmic;
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static unsigned int g_extinterrupt_flag = 0;
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static struct of_device_id of_hisi_pmic_match_tbl[] = {
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{
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.compatible = "hisilicon-hisi-pmic-spmi",
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},
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{ /* end */ }
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};
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/*
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* The PMIC register is only 8-bit.
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* Hisilicon SoC use hardware to map PMIC register into SoC mapping.
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* At here, we are accessing SoC register with 32-bit.
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*/
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u32 hisi_pmic_read(struct hisi_pmic *pmic, int reg)
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{
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u32 ret;
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u8 read_value = 0;
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struct spmi_device *pdev;
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if (NULL == g_pmic) {
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pr_err(" g_pmic is NULL\n");
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return 0;
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}
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pdev = to_spmi_device(g_pmic->dev);
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if (NULL == pdev) {
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pr_err("%s:pdev get failed!\n", __func__);
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return 0;
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}
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ret = spmi_ext_register_readl(pdev, reg, (unsigned char*)&read_value, 1);/*lint !e734 !e732 */
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if (ret) {
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pr_err("%s:spmi_ext_register_readl failed!\n", __func__);
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return ret;
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}
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return (u32)read_value;
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}
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EXPORT_SYMBOL(hisi_pmic_read);
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void hisi_pmic_write(struct hisi_pmic *pmic, int reg, u32 val)
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{
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u32 ret;
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struct spmi_device *pdev;
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if (NULL == g_pmic) {
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pr_err(" g_pmic is NULL\n");
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return;
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}
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pdev = to_spmi_device(g_pmic->dev);
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if (NULL == pdev) {
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pr_err("%s:pdev get failed!\n", __func__);
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return;
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}
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ret = spmi_ext_register_writel(pdev, reg, (unsigned char*)&val, 1);/*lint !e734 !e732 */
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if (ret) {
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pr_err("%s:spmi_ext_register_writel failed!\n", __func__);
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return ;
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}
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}
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EXPORT_SYMBOL(hisi_pmic_write);
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#ifdef CONFIG_HISI_DIEID
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u32 hisi_pmic_read_sub_pmu(u8 sid, int reg)
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{
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u32 ret;
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u8 read_value = 0;
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struct spmi_device *pdev;
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if(strstr(saved_command_line, "androidboot.swtype=factory"))
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{
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if (NULL == g_pmic) {
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pr_err(" g_pmic is NULL\n");
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return -1;/*lint !e570 */
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}
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pdev = to_spmi_device(g_pmic->dev);
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if (NULL == pdev) {
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pr_err("%s:pdev get failed!\n", __func__);
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return -1;/*lint !e570 */
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}
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ret = spmi_ext_register_readl(pdev->ctrl, sid, reg, (unsigned char*)&read_value, 1);/*lint !e734 !e732 */
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if (ret) {
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pr_err("%s:spmi_ext_register_readl failed!\n", __func__);
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return ret;
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}
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return (u32)read_value;
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}
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return 0;
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}
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EXPORT_SYMBOL(hisi_pmic_read_sub_pmu);
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void hisi_pmic_write_sub_pmu(u8 sid, int reg, u32 val)
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{
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u32 ret;
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struct spmi_device *pdev;
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if(strstr(saved_command_line, "androidboot.swtype=factory"))
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{
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if (NULL == g_pmic) {
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pr_err(" g_pmic is NULL\n");
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return;
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}
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pdev = to_spmi_device(g_pmic->dev);
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if (NULL == pdev) {
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pr_err("%s:pdev get failed!\n", __func__);
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return;
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}
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ret = spmi_ext_register_writel(pdev->ctrl, sid, reg, (unsigned char*)&val, 1);/*lint !e734 !e732 */
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if (ret) {
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pr_err("%s:spmi_ext_register_writel failed!\n", __func__);
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return ;
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}
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}
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return ;
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}
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EXPORT_SYMBOL(hisi_pmic_write_sub_pmu);
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#endif
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void hisi_pmic_rmw(struct hisi_pmic *pmic, int reg,
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u32 mask, u32 bits)
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{
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u32 data;
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unsigned long flags;
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if (NULL == g_pmic) {
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pr_err(" g_pmic is NULL\n");
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return;
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}
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spin_lock_irqsave(&g_pmic->lock, flags);
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data = hisi_pmic_read(pmic, reg) & ~mask;
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data |= mask & bits;
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hisi_pmic_write(pmic, reg, data);
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spin_unlock_irqrestore(&g_pmic->lock, flags);
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}
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EXPORT_SYMBOL(hisi_pmic_rmw);
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unsigned int hisi_pmic_reg_read(int addr)
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{
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return (unsigned int)hisi_pmic_read(g_pmic, addr);
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}
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EXPORT_SYMBOL(hisi_pmic_reg_read);
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void hisi_pmic_reg_write(int addr, int val)
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{
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hisi_pmic_write(g_pmic, addr, val);
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}
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EXPORT_SYMBOL(hisi_pmic_reg_write);
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void hisi_pmic_reg_write_lock(int addr, int val)
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{
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unsigned long flags;
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if (NULL == g_pmic) {
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pr_err(" g_pmic is NULL\n");
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return;
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}
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spin_lock_irqsave(&g_pmic->lock, flags);
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hisi_pmic_write(g_pmic, g_pmic->normal_lock.addr, g_pmic->normal_lock.val);
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hisi_pmic_write(g_pmic, g_pmic->debug_lock.addr, g_pmic->debug_lock.val);
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hisi_pmic_write(g_pmic, addr, val);
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hisi_pmic_write(g_pmic, g_pmic->normal_lock.addr, 0);
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hisi_pmic_write(g_pmic, g_pmic->debug_lock.addr, 0);
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spin_unlock_irqrestore(&g_pmic->lock, flags);
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}
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int hisi_pmic_array_read(int addr, char *buff, unsigned int len)
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{
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unsigned int i;
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if ((len > 32) || (NULL == buff)) {
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return -EINVAL;
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}
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/*
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* Here is a bug in the pmu die.
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* the coul driver will read 4 bytes,
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* but the ssi bus only read 1 byte, and the pmu die
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* will make sampling 1/10669us about vol cur,so the driver
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* read the data is not the same sampling
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*/
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for (i = 0; i < len; i++)
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{
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*(buff + i) = hisi_pmic_reg_read(addr+i);
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}
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return 0;
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}
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int hisi_pmic_array_write(int addr, char *buff, unsigned int len)
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{
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unsigned int i;
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if ((len > 32) || (NULL == buff)) {
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return -EINVAL;
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}
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for (i = 0; i < len; i++)
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{
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hisi_pmic_reg_write(addr+i, *(buff + i));
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}
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return 0;
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}
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static irqreturn_t hisi_irq_handler(int irq, void *data)
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{
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struct hisi_pmic *pmic = (struct hisi_pmic *)data;
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unsigned long pending;
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int i, offset;
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for (i = 0; i < pmic->irqarray; i++) {
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pending = hisi_pmic_reg_read((i + pmic->irq_addr.start_addr));
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pending &= HISI_MASK_FIELD;
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if (pending != 0) {
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pr_info("pending[%d]=0x%lx\n\r", i, pending);
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}
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hisi_pmic_reg_write((i + pmic->irq_addr.start_addr), pending);
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/*solve powerkey order*/
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if ((HISI_IRQ_KEY_NUM == i) && ((pending & HISI_IRQ_KEY_VALUE) == HISI_IRQ_KEY_VALUE)) {
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generic_handle_irq(pmic->irqs[HISI_IRQ_KEY_DOWN]);
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generic_handle_irq(pmic->irqs[HISI_IRQ_KEY_UP]);
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pending &= (~HISI_IRQ_KEY_VALUE);
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}
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if (pending) {
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for_each_set_bit(offset, &pending, HISI_BITS)
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generic_handle_irq(pmic->irqs[offset + i * HISI_BITS]);/*lint !e679 */
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}
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}
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/*Handle the second group irq if analysis the second group irq from dtsi*/
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if (1 == g_extinterrupt_flag){
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for (i = 0; i < pmic->irqarray1; i++) {
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pending = hisi_pmic_reg_read((i + pmic->irq_addr1.start_addr));
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pending &= HISI_MASK_FIELD;
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if (pending != 0) {
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pr_info("pending[%d]=0x%lx\n\r", i, pending);
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}
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hisi_pmic_reg_write((i + pmic->irq_addr1.start_addr), pending);
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if (pending) {
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for_each_set_bit(offset, &pending, HISI_BITS)
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generic_handle_irq(pmic->irqs[offset + (i+HISI_PMIC_FIRST_GROUP_INT_NUM) * HISI_BITS]);/*lint !e679 */
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}
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}
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}
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return IRQ_HANDLED;
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}
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static void hisi_irq_mask(struct irq_data *d)
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{
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struct hisi_pmic *pmic = irq_data_get_irq_chip_data(d);
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u32 data, offset;
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unsigned long flags;
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if (NULL == g_pmic) {
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pr_err(" g_pmic is NULL\n");
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return;
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}
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offset = (irqd_to_hwirq(d) >> 3);
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if (1==g_extinterrupt_flag){
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if ( offset < HISI_PMIC_FIRST_GROUP_INT_NUM)
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offset += pmic->irq_mask_addr.start_addr;
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else/*Change addr when irq num larger than 16 because interrupt addr is nonsequence*/
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offset = offset+(pmic->irq_mask_addr1.start_addr)-HISI_PMIC_FIRST_GROUP_INT_NUM;
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}else{
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offset += pmic->irq_mask_addr.start_addr;
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}
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spin_lock_irqsave(&g_pmic->lock, flags);
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data = hisi_pmic_reg_read(offset);
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data |= (1 << (irqd_to_hwirq(d) & 0x07));
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hisi_pmic_reg_write(offset, data);
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spin_unlock_irqrestore(&g_pmic->lock, flags);
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}
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static void hisi_irq_unmask(struct irq_data *d)
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{
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struct hisi_pmic *pmic = irq_data_get_irq_chip_data(d);
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u32 data, offset;
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unsigned long flags;
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if (NULL == g_pmic) {
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pr_err(" g_pmic is NULL\n");
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return;
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}
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offset = (irqd_to_hwirq(d) >> 3);
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if (1==g_extinterrupt_flag){
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if ( offset < HISI_PMIC_FIRST_GROUP_INT_NUM)
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offset += pmic->irq_mask_addr.start_addr;
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else
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offset = offset+(pmic->irq_mask_addr1.start_addr)-HISI_PMIC_FIRST_GROUP_INT_NUM;
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}else{
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offset += pmic->irq_mask_addr.start_addr;
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}
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spin_lock_irqsave(&g_pmic->lock, flags);
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data = hisi_pmic_reg_read(offset);
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data &= ~(1 << (irqd_to_hwirq(d) & 0x07)); /*lint !e502 */
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hisi_pmic_reg_write(offset, data);
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spin_unlock_irqrestore(&g_pmic->lock, flags);
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}
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static struct irq_chip hisi_pmu_irqchip = {
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.name = "hisi-irq",
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.irq_mask = hisi_irq_mask,
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.irq_unmask = hisi_irq_unmask,
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.irq_disable = hisi_irq_mask,
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.irq_enable = hisi_irq_unmask,
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};
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static int hisi_irq_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct hisi_pmic *pmic = d->host_data;
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irq_set_chip_and_handler_name(virq, &hisi_pmu_irqchip,
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handle_simple_irq, "hisi");
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irq_set_chip_data(virq, pmic);
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irq_set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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static struct irq_domain_ops hisi_domain_ops = {
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.map = hisi_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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/*lint -e570 -e64*/
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static int get_pmic_device_tree_data(struct device_node *np, struct hisi_pmic *pmic)
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{
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int ret = 0;
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/*get pmic irq num*/
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ret = of_property_read_u32_array(np, "hisilicon,hisi-pmic-irq-num",
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&(pmic->irqnum), 1);
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if (ret) {
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pr_err("no hisilicon,hisi-pmic-irq-num property set\n");
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ret = -ENODEV;
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return ret;
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}
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/*get pmic irq array number*/
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ret = of_property_read_u32_array(np, "hisilicon,hisi-pmic-irq-array",
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&(pmic->irqarray), 1);
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if (ret) {
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pr_err("no hisilicon,hisi-pmic-irq-array property set\n");
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ret = -ENODEV;
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return ret;
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}
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/*SOC_PMIC_IRQ_MASK_0_ADDR*/
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ret = of_property_read_u32_array(np, "hisilicon,hisi-pmic-irq-mask-addr",
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(int *)&pmic->irq_mask_addr, 2);
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if (ret) {
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pr_err("no hisilicon,hisi-pmic-irq-mask-addr property set\n");
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ret = -ENODEV;
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return ret;
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}
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/*SOC_PMIC_IRQ0_ADDR*/
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ret = of_property_read_u32_array(np, "hisilicon,hisi-pmic-irq-addr",
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(int *)&pmic->irq_addr, 2);
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if (ret) {
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pr_err("no hisilicon,hisi-pmic-irq-addr property set\n");
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ret = -ENODEV;
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return ret;
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}
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ret = of_property_read_u32_array(np, "hisilicon,hisi-pmic-vbus",
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(u32 *)&g_pmic_vbus, 2);
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if (ret) {
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pr_err("no hisilicon,hisi-pmic-vbus property\n");
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ret = -ENODEV;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*pmic lock*/
|
||||
ret = of_property_read_u32_array(np, "hisilicon,hisi-pmic-lock",
|
||||
(int *)&pmic->normal_lock, 2);
|
||||
if (ret) {
|
||||
pr_err("no hisilicon,hisi-pmic-lock property set\n");
|
||||
ret = -ENODEV;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*pmic debug lock*/
|
||||
ret = of_property_read_u32_array(np, "hisilicon,hisi-pmic-debug-lock",
|
||||
(int *)&pmic->debug_lock, 2);
|
||||
if (ret) {
|
||||
pr_err("no hisilicon,hisi-pmic-debug-lock property set\n");
|
||||
ret = -ENODEV;
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}/*lint -restore*/
|
||||
|
||||
|
||||
/*lint -e570 -e64*/
|
||||
static int get_pmic_device_tree_data1(struct device_node *np, struct hisi_pmic *pmic)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
/*get pmic irq num*/
|
||||
ret = of_property_read_u32_array(np, "hisilicon,hisi-pmic-irq-num1",
|
||||
&(pmic->irqnum1), 1);
|
||||
if (ret) {
|
||||
pr_err("no hisilicon,hisi-pmic-irq-num1 property set\n");
|
||||
ret = -ENODEV;
|
||||
pmic->irqnum1 = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*get pmic irq array number*/
|
||||
ret = of_property_read_u32_array(np, "hisilicon,hisi-pmic-irq-array1",
|
||||
&(pmic->irqarray1), 1);
|
||||
if (ret) {
|
||||
pr_err("no hisilicon,hisi-pmic-irq-array1 property set\n");
|
||||
ret = -ENODEV;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*SOC_PMIC_IRQ_MASK_0_ADDR*/
|
||||
ret = of_property_read_u32_array(np, "hisilicon,hisi-pmic-irq-mask-addr1",
|
||||
(int *)&pmic->irq_mask_addr1, 2);
|
||||
if (ret) {
|
||||
pr_err("no hisilicon,hisi-pmic-irq-mask-addr1 property set\n");
|
||||
ret = -ENODEV;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*SOC_PMIC_IRQ0_ADDR*/
|
||||
ret = of_property_read_u32_array(np, "hisilicon,hisi-pmic-irq-addr1",
|
||||
(int *)&pmic->irq_addr1, 2);
|
||||
if (ret) {
|
||||
pr_err("no hisilicon,hisi-pmic-irq-addr1 property set\n");
|
||||
ret = -ENODEV;
|
||||
return ret;
|
||||
}
|
||||
|
||||
g_extinterrupt_flag = 1;
|
||||
return ret;
|
||||
}/*lint -restore*/
|
||||
|
||||
int hisi_get_pmic_irq_byname(unsigned int pmic_irq_list)
|
||||
{
|
||||
if ( NULL == g_pmic ) {
|
||||
pr_err("[%s]g_pmic is NULL\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (pmic_irq_list > (unsigned int)g_pmic->irqnum) {
|
||||
pr_err("[%s]input pmic irq number is error.\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
pr_info("%s:g_pmic->irqs[%d]=%d\n", __func__, pmic_irq_list, g_pmic->irqs[pmic_irq_list]);
|
||||
return (int)g_pmic->irqs[pmic_irq_list];
|
||||
}
|
||||
EXPORT_SYMBOL(hisi_get_pmic_irq_byname);
|
||||
|
||||
int hisi_pmic_get_vbus_status(void)
|
||||
{
|
||||
if (0 == g_pmic_vbus.addr)
|
||||
return -1;
|
||||
|
||||
if (hisi_pmic_reg_read(g_pmic_vbus.addr) & BIT(g_pmic_vbus.bit))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(hisi_pmic_get_vbus_status);
|
||||
|
||||
static void hisi_pmic_irq_prc(struct hisi_pmic *pmic)
|
||||
{
|
||||
int i;
|
||||
for (i = 0 ; i < pmic->irq_mask_addr.array; i++) {
|
||||
hisi_pmic_write(pmic, pmic->irq_mask_addr.start_addr + i, HISI_MASK_STATE);
|
||||
}
|
||||
|
||||
for (i = 0 ; i < pmic->irq_addr.array; i++) {
|
||||
unsigned int pending = hisi_pmic_read(pmic, pmic->irq_addr.start_addr + i);
|
||||
pr_debug("PMU IRQ address value:irq[0x%x] = 0x%x\n", pmic->irq_addr.start_addr + i, pending);
|
||||
hisi_pmic_write(pmic, pmic->irq_addr.start_addr + i, HISI_MASK_STATE);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static void hisi_pmic_irq1_prc(struct hisi_pmic *pmic)
|
||||
{
|
||||
int i;
|
||||
if(1 == g_extinterrupt_flag){
|
||||
for (i = 0 ; i < pmic->irq_mask_addr1.array; i++) {
|
||||
hisi_pmic_write(pmic, pmic->irq_mask_addr1.start_addr + i, HISI_MASK_STATE);
|
||||
}
|
||||
|
||||
for (i = 0 ; i < pmic->irq_addr1.array; i++) {
|
||||
unsigned int pending1 = hisi_pmic_read(pmic, pmic->irq_addr1.start_addr + i);
|
||||
pr_debug("PMU IRQ address1 value:irq[0x%x] = 0x%x\n", pmic->irq_addr1.start_addr + i, pending1);
|
||||
hisi_pmic_write(pmic, pmic->irq_addr1.start_addr + i, HISI_MASK_STATE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int hisi_pmic_probe(struct spmi_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct hisi_pmic *pmic = NULL;
|
||||
enum of_gpio_flags flags;
|
||||
int ret = 0;
|
||||
int i;
|
||||
unsigned int fpga_flag = 0;
|
||||
unsigned int virq;
|
||||
|
||||
pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
|
||||
if (!pmic) {
|
||||
dev_err(dev, "cannot allocate hisi_pmic device info\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/*TODO: get pmic dts info*/
|
||||
ret = get_pmic_device_tree_data(np, pmic);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Error reading hisi pmic dts \n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*get pmic dts the second group irq*/
|
||||
ret = get_pmic_device_tree_data1(np, pmic);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "the platform don't support ext-interrupt.\n");
|
||||
}
|
||||
|
||||
/* TODO: get and enable clk request */
|
||||
spin_lock_init(&pmic->lock);
|
||||
|
||||
pmic->dev = dev;
|
||||
g_pmic = pmic;
|
||||
ret = of_property_read_u32_array(np, "hisilicon,pmic_fpga_flag", &fpga_flag, 1);
|
||||
if (ret) {
|
||||
pr_err("no hisilicon,pmic_fpga_flag property set\n");
|
||||
}
|
||||
if (PMIC_FPGA_FLAG == fpga_flag) {
|
||||
goto after_irq_register;
|
||||
}
|
||||
|
||||
pmic->gpio = of_get_gpio_flags(np, 0, &flags);
|
||||
if (pmic->gpio < 0)
|
||||
return pmic->gpio;
|
||||
|
||||
if (!gpio_is_valid(pmic->gpio))
|
||||
return -EINVAL;
|
||||
|
||||
ret = gpio_request_one(pmic->gpio, GPIOF_IN, "pmic");
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to request gpio%d\n", pmic->gpio);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pmic->irq = gpio_to_irq(pmic->gpio);
|
||||
|
||||
/* mask && clear IRQ status */
|
||||
hisi_pmic_irq_prc(pmic);
|
||||
/*clear && mask the new adding irq*/
|
||||
hisi_pmic_irq1_prc(pmic);
|
||||
|
||||
pmic->irqnum += pmic->irqnum1;
|
||||
|
||||
pmic->irqs = (unsigned int *)devm_kmalloc(dev, pmic->irqnum * sizeof(int), GFP_KERNEL);
|
||||
if (!pmic->irqs) {
|
||||
pr_err("%s:Failed to alloc memory for pmic irq number!\n", __func__);
|
||||
goto irq_malloc;
|
||||
}
|
||||
memset(pmic->irqs, 0, pmic->irqnum);
|
||||
|
||||
pmic->domain = irq_domain_add_simple(np, pmic->irqnum, 0,
|
||||
&hisi_domain_ops, pmic);
|
||||
if (!pmic->domain) {
|
||||
dev_err(dev, "failed irq domain add simple!\n");
|
||||
ret = -ENODEV;
|
||||
goto irq_domain;
|
||||
}
|
||||
|
||||
for (i = 0; i < pmic->irqnum; i++) {
|
||||
virq = irq_create_mapping(pmic->domain, i);
|
||||
if (virq == NO_IRQ) {
|
||||
pr_debug("Failed mapping hwirq\n");
|
||||
ret = -ENOSPC;
|
||||
goto irq_create_mapping;
|
||||
}
|
||||
pmic->irqs[i] = virq;
|
||||
pr_info("[%s]. pmic->irqs[%d] = %d\n", __func__, i, pmic->irqs[i]);
|
||||
}
|
||||
|
||||
ret = request_threaded_irq(pmic->irq, hisi_irq_handler, NULL,
|
||||
IRQF_TRIGGER_LOW | IRQF_SHARED | IRQF_NO_SUSPEND,
|
||||
"pmic", pmic);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "could not claim pmic %d\n", ret);
|
||||
ret = -ENODEV;
|
||||
goto request_theaded_irq;
|
||||
}
|
||||
|
||||
after_irq_register:
|
||||
return 0;
|
||||
|
||||
|
||||
request_theaded_irq:
|
||||
irq_create_mapping:
|
||||
irq_domain:
|
||||
irq_malloc:
|
||||
gpio_free(pmic->gpio);
|
||||
g_pmic = NULL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void hisi_pmic_remove(struct spmi_device *pdev)
|
||||
{
|
||||
|
||||
struct hisi_pmic *pmic = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
free_irq(pmic->irq, pmic);
|
||||
gpio_free(pmic->gpio);
|
||||
devm_kfree(&pdev->dev, pmic);
|
||||
|
||||
}
|
||||
static int hisi_pmic_suspend(struct device *dev, pm_message_t state)
|
||||
{
|
||||
struct hisi_pmic *pmic = dev_get_drvdata(dev);
|
||||
|
||||
if (NULL == pmic) {
|
||||
pr_err("%s:pmic is NULL\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pr_info("%s:+\n", __func__);
|
||||
pr_info("%s:-\n", __func__);
|
||||
|
||||
return 0;
|
||||
}/*lint !e715 */
|
||||
|
||||
static int hisi_pmic_resume(struct device *dev)
|
||||
{
|
||||
struct hisi_pmic *pmic = dev_get_drvdata(dev);
|
||||
|
||||
if (NULL == pmic) {
|
||||
pr_err("%s:pmic is NULL\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pr_info("%s:+\n", __func__);
|
||||
pr_info("%s:-\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
MODULE_DEVICE_TABLE(spmi, pmic_spmi_id);
|
||||
static struct spmi_driver hisi_pmic_driver = {
|
||||
.driver = {
|
||||
.name = "hisi_pmic",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_hisi_pmic_match_tbl,
|
||||
.suspend = hisi_pmic_suspend,
|
||||
.resume = hisi_pmic_resume,
|
||||
},
|
||||
.probe = hisi_pmic_probe,
|
||||
.remove = hisi_pmic_remove,
|
||||
};
|
||||
|
||||
static int __init hisi_pmic_init(void)
|
||||
{
|
||||
return spmi_driver_register(&hisi_pmic_driver);
|
||||
}
|
||||
|
||||
static void __exit hisi_pmic_exit(void)
|
||||
{
|
||||
spmi_driver_unregister(&hisi_pmic_driver);
|
||||
}
|
||||
|
||||
|
||||
subsys_initcall_sync(hisi_pmic_init);
|
||||
module_exit(hisi_pmic_exit);
|
||||
|
||||
MODULE_DESCRIPTION("PMIC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
/*
|
||||
* Header file for device driver Hi6421 PMIC
|
||||
*
|
||||
* Copyright (c) 2013 Linaro Ltd.
|
||||
* Copyright (C) 2011 Hisilicon.
|
||||
*
|
||||
* Guodong Xu <guodong.xu@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef __HISI_PMIC_H
|
||||
#define __HISI_PMIC_H
|
||||
|
||||
#include <linux/irqdomain.h>
|
||||
|
||||
#define HISI_REGS_ENA_PROTECT_TIME (0) /* in microseconds */
|
||||
#define HISI_ECO_MODE_ENABLE (1)
|
||||
#define HISI_ECO_MODE_DISABLE (0)
|
||||
|
||||
typedef int (*pmic_ocp_callback)(char *);
|
||||
extern int hisi_pmic_special_ocp_register(char *power_name, pmic_ocp_callback handler);
|
||||
|
||||
struct irq_mask_info {
|
||||
int start_addr;
|
||||
int array;
|
||||
};
|
||||
|
||||
struct irq_info {
|
||||
int start_addr;
|
||||
int array;
|
||||
};
|
||||
|
||||
struct bit_info {
|
||||
int addr;
|
||||
int bit;
|
||||
};
|
||||
|
||||
struct write_lock {
|
||||
int addr;
|
||||
int val;
|
||||
};
|
||||
|
||||
struct hisi_pmic {
|
||||
struct resource *res;
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
spinlock_t lock;
|
||||
struct irq_domain *domain;
|
||||
int irq;
|
||||
int gpio;
|
||||
unsigned int *irqs;
|
||||
int irqnum;
|
||||
int irqarray;
|
||||
struct irq_mask_info irq_mask_addr;
|
||||
struct irq_info irq_addr;
|
||||
int irqnum1;
|
||||
int irqarray1;
|
||||
struct irq_mask_info irq_mask_addr1;
|
||||
struct irq_info irq_addr1;
|
||||
struct write_lock normal_lock;
|
||||
struct write_lock debug_lock;
|
||||
};
|
||||
|
||||
/* 0:disable; 1:enable */
|
||||
unsigned int get_uv_mntn_status(void);
|
||||
void clear_uv_mntn_resered_reg_bit(void);
|
||||
void set_uv_mntn_resered_reg_bit(void);
|
||||
|
||||
#if defined(CONFIG_HISI_PMIC) || defined(CONFIG_HISI_PMIC_PMU_SPMI)
|
||||
/* Register Access Helpers */
|
||||
u32 hisi_pmic_read(struct hisi_pmic *pmic, int reg);
|
||||
void hisi_pmic_write(struct hisi_pmic *pmic, int reg, u32 val);
|
||||
void hisi_pmic_rmw(struct hisi_pmic *pmic, int reg, u32 mask, u32 bits);
|
||||
unsigned int hisi_pmic_reg_read(int addr);
|
||||
void hisi_pmic_reg_write(int addr, int val);
|
||||
void hisi_pmic_reg_write_lock(int addr, int val);
|
||||
int hisi_pmic_array_read(int addr, char *buff, unsigned int len);
|
||||
int hisi_pmic_array_write(int addr, char *buff, unsigned int len);
|
||||
extern int hisi_get_pmic_irq_byname(unsigned int pmic_irq_list);
|
||||
extern int hisi_pmic_get_vbus_status(void);
|
||||
#if defined(CONFIG_HISI_DIEID)
|
||||
u32 hisi_pmic_read_sub_pmu(u8 sid ,int reg);
|
||||
void hisi_pmic_write_sub_pmu(u8 sid ,int reg, u32 val);
|
||||
#endif
|
||||
#else
|
||||
static inline u32 hisi_pmic_read(struct hisi_pmic *pmic, int reg) { return 0; }
|
||||
static inline void hisi_pmic_write(struct hisi_pmic *pmic, int reg, u32 val) {}
|
||||
static inline void hisi_pmic_rmw(struct hisi_pmic *pmic, int reg, u32 mask, u32 bits) {}
|
||||
static inline unsigned int hisi_pmic_reg_read(int addr) { return 0; }
|
||||
static inline void hisi_pmic_reg_write(int addr, int val) {}
|
||||
static inline void hisi_pmic_reg_write_lock(int addr, int val) {}
|
||||
static inline int hisi_pmic_array_read(int addr, char *buff, unsigned int len) { return 0; }
|
||||
static inline int hisi_pmic_array_write(int addr, char *buff, unsigned int len) { return 0; }
|
||||
static inline int hisi_get_pmic_irq_byname(unsigned int pmic_irq_list) { return -1; }
|
||||
static inline int hisi_pmic_get_vbus_status(void) { return 1; }
|
||||
static inline u32 hisi_pmic_read_sub_pmu(u8 sid ,int reg) { return 0; }
|
||||
static inline void hisi_pmic_write_sub_pmu(u8 sid ,int reg, u32 val) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HISI_HI6421V500_PMU
|
||||
enum pmic_irq_list {
|
||||
POR_D45MR = 0,
|
||||
VBUS_CONNECT,
|
||||
VBUS_DISCONNECT,
|
||||
ALARMON_R,
|
||||
HOLD_6S,
|
||||
HOLD_1S,
|
||||
POWERKEY_UP,
|
||||
POWERKEY_DOWN,
|
||||
OCP_SCP_R,
|
||||
COUL_R,
|
||||
VSYS_OV,
|
||||
VSYS_UV,
|
||||
VSYS_PWROFF_ABS,
|
||||
VSYS_PWROFF_DEB,
|
||||
THSD_OTMP140,
|
||||
THSD_OTMP125,
|
||||
HRESETN,
|
||||
SIM0_HPD_R = 24,
|
||||
SIM0_HPD_F,
|
||||
SIM0_HPD_H,
|
||||
SIM0_HPD_L,
|
||||
SIM1_HPD_R,
|
||||
SIM1_HPD_F,
|
||||
SIM1_HPD_H,
|
||||
SIM1_HPD_L,
|
||||
PMIC_IRQ_LIST_MAX,
|
||||
};
|
||||
#else
|
||||
enum pmic_irq_list {
|
||||
OTMP = 0,
|
||||
VBUS_CONNECT,
|
||||
VBUS_DISCONNECT,
|
||||
ALARMON_R,
|
||||
HOLD_6S,
|
||||
HOLD_1S,
|
||||
POWERKEY_UP,
|
||||
POWERKEY_DOWN,
|
||||
OCP_SCP_R,
|
||||
COUL_R,
|
||||
SIM0_HPD_R,
|
||||
SIM0_HPD_F,
|
||||
SIM1_HPD_R,
|
||||
SIM1_HPD_F,
|
||||
PMIC_IRQ_LIST_MAX,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HISI_SR_DEBUG
|
||||
extern void get_ip_regulator_state(void);
|
||||
#endif
|
||||
#endif /* __HISI_PMIC_H */
|
||||
|
||||
Loading…
Reference in New Issue