mirror of https://gitee.com/openkylin/linux.git
staging: comedi: plx9052.h: document the CNTRL register
Add defines for the PLX 9052 CNTRL register defines and use them instead of the magic numbers in the me4000 driver Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
58af6b926e
commit
4564cfd052
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@ -170,19 +170,6 @@ broken.
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#define ME4000_AO_DEMUX_ADJUST_VALUE 0x4c
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#define ME4000_AI_SAMPLE_COUNTER_REG 0xc0
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/*
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* PLX Register map and bit defines
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*/
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#define PLX_ICR 0x50
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#define PLX_ICR_BIT_EEPROM_CLOCK_SET (1 << 24)
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#define PLX_ICR_BIT_EEPROM_CHIP_SELECT (1 << 25)
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#define PLX_ICR_BIT_EEPROM_WRITE (1 << 26)
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#define PLX_ICR_BIT_EEPROM_READ (1 << 27)
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#define PLX_ICR_BIT_EEPROM_VALID (1 << 28)
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#define PLX_ICR_MASK_EEPROM (0x1f << 24)
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#define EEPROM_DELAY 1
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#define ME4000_AI_FIFO_COUNT 2048
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#define ME4000_AI_MIN_TICKS 66
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@ -382,9 +369,9 @@ static int xilinx_download(struct comedi_device *dev)
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outl(PLX9052_INTCSR_LI2POL, info->plx_regbase + PLX9052_INTCSR);
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/* Set /CS and /WRITE of the Xilinx */
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value = inl(info->plx_regbase + PLX_ICR);
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value |= 0x100;
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outl(value, info->plx_regbase + PLX_ICR);
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value = inl(info->plx_regbase + PLX9052_CNTRL);
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value |= PLX9052_CNTRL_UIO2_DATA;
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outl(value, info->plx_regbase + PLX9052_CNTRL);
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/* Init Xilinx with CS1 */
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inb(xilinx_iobase + 0xC8);
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@ -398,9 +385,9 @@ static int xilinx_download(struct comedi_device *dev)
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}
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/* Reset /CS and /WRITE of the Xilinx */
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value = inl(info->plx_regbase + PLX_ICR);
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value &= ~0x100;
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outl(value, info->plx_regbase + PLX_ICR);
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value = inl(info->plx_regbase + PLX9052_CNTRL);
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value &= ~PLX9052_CNTRL_UIO2_DATA;
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outl(value, info->plx_regbase + PLX9052_CNTRL);
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if (FIRMWARE_NOT_AVAILABLE) {
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dev_err(dev->class_dev,
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"xilinx firmware unavailable due to licensing, aborting");
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@ -416,7 +403,7 @@ static int xilinx_download(struct comedi_device *dev)
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udelay(10);
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/* Check if BUSY flag is low */
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if (inl(info->plx_regbase + PLX_ICR) & 0x20) {
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if (inl(info->plx_regbase + PLX9052_CNTRL) & PLX9052_CNTRL_UIO1_DATA) {
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dev_err(dev->class_dev,
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"Xilinx is still busy (idx = %d)\n",
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idx);
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@ -426,7 +413,7 @@ static int xilinx_download(struct comedi_device *dev)
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}
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/* If done flag is high download was successful */
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if (inl(info->plx_regbase + PLX_ICR) & 0x4) {
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if (inl(info->plx_regbase + PLX9052_CNTRL) & PLX9052_CNTRL_UIO0_DATA) {
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} else {
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dev_err(dev->class_dev, "DONE flag is not set\n");
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dev_err(dev->class_dev, "Download not successful\n");
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@ -434,9 +421,9 @@ static int xilinx_download(struct comedi_device *dev)
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}
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/* Set /CS and /WRITE */
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value = inl(info->plx_regbase + PLX_ICR);
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value |= 0x100;
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outl(value, info->plx_regbase + PLX_ICR);
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value = inl(info->plx_regbase + PLX9052_CNTRL);
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value |= PLX9052_CNTRL_UIO2_DATA;
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outl(value, info->plx_regbase + PLX9052_CNTRL);
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return 0;
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}
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@ -448,11 +435,11 @@ static void me4000_reset(struct comedi_device *dev)
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int chan;
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/* Make a hardware reset */
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val = inl(info->plx_regbase + PLX_ICR);
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val |= 0x40000000;
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outl(val, info->plx_regbase + PLX_ICR);
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val &= ~0x40000000;
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outl(val , info->plx_regbase + PLX_ICR);
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val = inl(info->plx_regbase + PLX9052_CNTRL);
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val |= PLX9052_CNTRL_PCI_RESET;
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outl(val, info->plx_regbase + PLX9052_CNTRL);
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val &= ~PLX9052_CNTRL_PCI_RESET;
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outl(val , info->plx_regbase + PLX9052_CNTRL);
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/* 0x8000 to the DACs means an output voltage of 0V */
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for (chan = 0; chan < 4; chan++)
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@ -44,4 +44,41 @@
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#define PLX9052_INTCSR_LI2CLRINT (1 << 11) /* LI2 clear int */
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#define PLX9052_INTCSR_ISAMODE (1 << 12) /* ISA interface mode */
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/*
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* CNTRL - User I/O, Direct Slave Response, Serial EEPROM, and
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* Initialization Control register
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*/
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#define PLX9052_CNTRL 0x50
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#define PLX9052_CNTRL_WAITO (1 << 0) /* UIO0 or WAITO# select */
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#define PLX9052_CNTRL_UIO0_DIR (1 << 1) /* UIO0 direction */
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#define PLX9052_CNTRL_UIO0_DATA (1 << 2) /* UIO0 data */
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#define PLX9052_CNTRL_LLOCKO (1 << 3) /* UIO1 or LLOCKo# select */
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#define PLX9052_CNTRL_UIO1_DIR (1 << 4) /* UIO1 direction */
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#define PLX9052_CNTRL_UIO1_DATA (1 << 5) /* UIO1 data */
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#define PLX9052_CNTRL_CS2 (1 << 6) /* UIO2 or CS2# select */
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#define PLX9052_CNTRL_UIO2_DIR (1 << 7) /* UIO2 direction */
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#define PLX9052_CNTRL_UIO2_DATA (1 << 8) /* UIO2 data */
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#define PLX9052_CNTRL_CS3 (1 << 9) /* UIO3 or CS3# select */
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#define PLX9052_CNTRL_UIO3_DIR (1 << 10) /* UIO3 direction */
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#define PLX9052_CNTRL_UIO3_DATA (1 << 11) /* UIO3 data */
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#define PLX9052_CNTRL_PCIBAR01 (0 << 12) /* bar 0 (mem) and 1 (I/O) */
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#define PLX9052_CNTRL_PCIBAR0 (1 << 12) /* bar 0 (mem) only */
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#define PLX9052_CNTRL_PCIBAR1 (2 << 12) /* bar 1 (I/O) only */
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#define PLX9052_CNTRL_PCI2_1_FEATURES (1 << 14) /* PCI r2.1 features enabled */
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#define PLX9052_CNTRL_PCI_R_W_FLUSH (1 << 15) /* read w/write flush mode */
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#define PLX9052_CNTRL_PCI_R_NO_FLUSH (1 << 16) /* read no flush mode */
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#define PLX9052_CNTRL_PCI_R_NO_WRITE (1 << 17) /* read no write mode */
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#define PLX9052_CNTRL_PCI_W_RELEASE (1 << 18) /* write release bus mode */
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#define PLX9052_CNTRL_RETRY_CLKS(x) (((x) & 0xf) << 19) /* slave retry clks */
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#define PLX9052_CNTRL_LOCK_ENAB (1 << 23) /* slave LOCK# enable */
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#define PLX9052_CNTRL_EEPROM_MASK (0x1f << 24) /* EEPROM bits */
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#define PLX9052_CNTRL_EEPROM_CLK (1 << 24) /* EEPROM clock */
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#define PLX9052_CNTRL_EEPROM_CS (1 << 25) /* EEPROM chip select */
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#define PLX9052_CNTRL_EEPROM_DOUT (1 << 26) /* EEPROM write bit */
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#define PLX9052_CNTRL_EEPROM_DIN (1 << 27) /* EEPROM read bit */
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#define PLX9052_CNTRL_EEPROM_PRESENT (1 << 28) /* EEPROM present */
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#define PLX9052_CNTRL_RELOAD_CFG (1 << 29) /* reload configuration */
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#define PLX9052_CNTRL_PCI_RESET (1 << 30) /* PCI adapter reset */
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#define PLX9052_CNTRL_MASK_REV (1 << 31) /* mask revision */
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#endif /* _PLX9052_H_ */
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