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arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable() 

__flush_tlb_[kernel_]pgtable() rely on set_pXd() having a DSB after
writing the new table entry and therefore avoid the barrier prior to the
TLBI instruction.

In preparation for delaying our walk-cache invalidation on the unmap()
path, move the DSB into the TLB invalidation routines.

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Will Deacon 2018-08-22 21:40:30 +01:00 committed by Catalin Marinas
parent 6899a4c82f
commit 45a284bc5e
1 changed files with 2 additions and 0 deletions
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2
arch/arm64/include/asm/tlbflush.h
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@ -213,6 +213,7 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm,
{ {
unsigned long addr = __TLBI_VADDR(uaddr, ASID(mm)); unsigned long addr = __TLBI_VADDR(uaddr, ASID(mm));
dsb(ishst);
__tlbi(vae1is, addr); __tlbi(vae1is, addr);
__tlbi_user(vae1is, addr); __tlbi_user(vae1is, addr);
dsb(ish); dsb(ish);
@ -222,6 +223,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr)
{ {
unsigned long addr = __TLBI_VADDR(kaddr, 0); unsigned long addr = __TLBI_VADDR(kaddr, 0);
dsb(ishst);
__tlbi(vaae1is, addr); __tlbi(vaae1is, addr);
dsb(ish); dsb(ish);
} }