From b7a3768b6b7ceac8d8d176fad15b9542a4ccc3e8 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 5 May 2017 11:55:08 +0200 Subject: [PATCH 01/20] arm64: dts: marvell: add clocks for Armada AP806 XOR engines The XORv2 engines in the AP side of the Armada 7K/8K SoCs are using the AP MS core clock as input, so this commit adds the appropriate clocks properties. Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index fe41bf9c301e..9b9e36a627d8 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -159,6 +159,7 @@ xor@400000 { reg = <0x400000 0x1000>, <0x410000 0x1000>; msi-parent = <&gic_v2m0>; + clocks = <&ap_syscon 3>; dma-coherent; }; @@ -167,6 +168,7 @@ xor@420000 { reg = <0x420000 0x1000>, <0x430000 0x1000>; msi-parent = <&gic_v2m0>; + clocks = <&ap_syscon 3>; dma-coherent; }; @@ -175,6 +177,7 @@ xor@440000 { reg = <0x440000 0x1000>, <0x450000 0x1000>; msi-parent = <&gic_v2m0>; + clocks = <&ap_syscon 3>; dma-coherent; }; @@ -183,6 +186,7 @@ xor@460000 { reg = <0x460000 0x1000>, <0x470000 0x1000>; msi-parent = <&gic_v2m0>; + clocks = <&ap_syscon 3>; dma-coherent; }; From 5298304102d12277888be6cc3fa1f333f7cc3f65 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 16 May 2017 14:45:30 +0100 Subject: [PATCH 02/20] arm64: dts: marvell: mcbin: add sdhci Add sdhci support for MACCHIATOBin boards. This uses the AP806 SDHCI for eMMC and CP110 master for the SD card slot. Signed-off-by: Russell King Signed-off-by: Gregory CLEMENT --- .../boot/dts/marvell/armada-8040-mcbin.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts index f7bb0cc03147..100861aa7afd 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts @@ -95,6 +95,21 @@ &uart0 { status = "okay"; }; +&ap_sdhci0 { + bus-width = <8>; + /* + * Not stable in HS modes - phy needs "more calibration", so add + * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. + */ + marvell,xenon-phy-slow-mode; + no-1-8-v; + no-sd; + no-sdio; + non-removable; + status = "okay"; + vqmmc-supply = <&v_vddo_h>; +}; + &cpm_i2c0 { clock-frequency = <100000>; status = "okay"; @@ -105,6 +120,14 @@ &cpm_sata0 { status = "okay"; }; +&cpm_sdhci0 { + /* U6 */ + broken-cd; + bus-width = <4>; + status = "okay"; + vqmmc-supply = <&v_3_3>; +}; + &cpm_usb3_0 { /* J38? - USB2.0 only */ status = "okay"; From 4f08187d8cc97ada0992f855ad8d98c75bd7bb8d Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Tue, 16 May 2017 01:28:33 +0200 Subject: [PATCH 03/20] arm64: dts: marvell: add second 1G port on the Armada 8040 DB Armada 8040 DB is equipped with 4 (2x 10G SFI + 2x 1G RGMII) ethernet ports of which only one was hitherto enabled. Because currently mvpp2 driver is capable of supporting only 1G RGMII/SGMII, enable second port from CP slave HW block. Signed-off-by: Marcin Wojtas Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-8040-db.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index dc0d084005b2..3cde649f96e4 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -169,6 +169,22 @@ &cps_usb3_1 { status = "okay"; }; +&cps_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cps_ethernet { + status = "okay"; +}; + +&cps_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + &ap_sdhci0 { status = "okay"; bus-width = <4>; From 952eaa509dee29db9e3ac8b45c2087450a7ded10 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 31 May 2017 16:07:27 +0200 Subject: [PATCH 04/20] arm64: dts: marvell: remove clock-output-names on ap806 The clock-output-names of the ap806-system-controller node are not used anymore, so remove them. Reviewed-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 9b9e36a627d8..5d4f71f94b5b 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -248,10 +248,6 @@ ap_syscon: system-controller@6f4000 { compatible = "marvell,ap806-system-controller", "syscon"; #clock-cells = <1>; - clock-output-names = "ap-cpu-cluster-0", - "ap-cpu-cluster-1", - "ap-fixed", "ap-mss", - "ap-emmc"; reg = <0x6f4000 0x1000>; }; }; From 3675fb5980bf98136aa7e49f373faf57a19e3ba0 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 31 May 2017 16:07:28 +0200 Subject: [PATCH 05/20] arm64: dts: marvell: use new binding for the system controller on ap806 The new binding for the system controller on ap806 moved the clock into a subnode. This preliminary step will allow to add gpio and pinctrl subnodes Reviewed-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 5d4f71f94b5b..ff1964d314de 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -197,7 +197,7 @@ spi0: spi@510600 { #size-cells = <0>; cell-index = <0>; interrupts = ; - clocks = <&ap_syscon 3>; + clocks = <&ap_clk 3>; status = "disabled"; }; @@ -208,7 +208,7 @@ i2c0: i2c@511000 { #size-cells = <0>; interrupts = ; timeout-ms = <1000>; - clocks = <&ap_syscon 3>; + clocks = <&ap_clk 3>; status = "disabled"; }; @@ -218,7 +218,7 @@ uart0: serial@512000 { reg-shift = <2>; interrupts = ; reg-io-width = <1>; - clocks = <&ap_syscon 3>; + clocks = <&ap_clk 3>; status = "disabled"; }; @@ -228,7 +228,7 @@ uart1: serial@512100 { reg-shift = <2>; interrupts = ; reg-io-width = <1>; - clocks = <&ap_syscon 3>; + clocks = <&ap_clk 3>; status = "disabled"; }; @@ -238,17 +238,20 @@ ap_sdhci0: sdhci@6e0000 { reg = <0x6e0000 0x300>; interrupts = ; clock-names = "core"; - clocks = <&ap_syscon 4>; + clocks = <&ap_clk 4>; dma-coherent; marvell,xenon-phy-slow-mode; status = "disabled"; }; ap_syscon: system-controller@6f4000 { - compatible = "marvell,ap806-system-controller", - "syscon"; - #clock-cells = <1>; + compatible = "syscon", "simple-mfd"; reg = <0x6f4000 0x1000>; + + ap_clk: clock { + compatible = "marvell,ap806-clock"; + #clock-cells = <1>; + }; }; }; }; From e21a3b543701c2781ff689c640a1cf73d7baf7d1 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 6 Jun 2017 11:57:15 +0200 Subject: [PATCH 06/20] arm64: dts: marvell: cp110: add required clocks for mdio interface Add the three required clocks for the MDIO interface to be functional on Armada 8k platforms. Without this, the CPU hangs, causing RCU stalls or the system to become unresponsive. Signed-off-by: Russell King [Thomas: - remove mg_core_clock, since it's a parent of mg_clock - also add clock references to the slave CP mdio instance] Signed-off-by: Thomas Petazzoni Tested-by: Marc Zyngier Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index ac8df5201cd6..576e825585c9 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -94,6 +94,7 @@ cpm_mdio: mdio@12a200 { #size-cells = <0>; compatible = "marvell,orion-mdio"; reg = <0x12a200 0x10>; + clocks = <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>; }; cpm_syscon0: system-controller@440000 { diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 7740a75a8230..797208a11f9d 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -101,6 +101,7 @@ cps_mdio: mdio@12a200 { #size-cells = <0>; compatible = "marvell,orion-mdio"; reg = <0x12a200 0x10>; + clocks = <&cps_syscon0 1 9>, <&cps_syscon0 1 5>; }; cps_syscon0: system-controller@440000 { From 2a32465912d49024653f2c1a5117f3323be2b65b Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 8 Jun 2017 11:42:43 +0100 Subject: [PATCH 07/20] arm64: dts: marvell: 8040-mcbin: Enable 1GB Ethernet Enable the 1GB Ethernet interface that lives on the slave CP110, with its corresponding phy (that oddly lives on the master CP110). Signed-off-by: Marc Zyngier Signed-off-by: Gregory CLEMENT --- .../boot/dts/marvell/armada-8040-mcbin.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts index 100861aa7afd..fe56efcfcefe 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts @@ -115,6 +115,12 @@ &cpm_i2c0 { status = "okay"; }; +&cpm_mdio { + ge_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + &cpm_sata0 { /* CPM Lane 0 - U29 */ status = "okay"; @@ -138,6 +144,17 @@ &cpm_usb3_1 { status = "okay"; }; +&cps_ethernet { + status = "okay"; +}; + +&cps_eth1 { + /* CPS Lane 0 - J5 (Gigabit RJ45) */ + status = "okay"; + phy = <&ge_phy>; + phy-mode = "sgmii"; +}; + &cps_sata0 { /* CPS Lane 1 - U32 */ /* CPS Lane 3 - U31 */ From b1a97f86b7359da7bbd7a8dd2900d62352c04644 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Wed, 24 May 2017 16:10:33 +0200 Subject: [PATCH 08/20] arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k The EIP197 cryptographic engine supports 64 bits address width but is limited to 40 bits on 7k/8k. Add a dma-mask property in the cryptographic engine nodes to reflect this. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 576e825585c9..e02ac90f7fdf 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -242,6 +242,7 @@ cpm_crypto: crypto@800000 { interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cpm_syscon0 1 26>; + dma-mask = <0xff 0xffffffff>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 797208a11f9d..7468fe00fc37 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -232,6 +232,7 @@ cps_crypto: crypto@800000 { interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cps_syscon0 1 26>; + dma-mask = <0xff 0xffffffff>; status = "disabled"; }; }; From 3c6912cdc88f0837caf1a55dec5845fc2f84be3a Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 8 Jun 2017 12:04:54 +0200 Subject: [PATCH 09/20] arm64: dts: marvell: explicitly enable the mdio nodes for 7k/8k DB Explicitly enable the MDIO nodes in the Marvell Armada 7k DB and Marvell Armada 8k DB. This is needed as the MDIO nodes will be disabled in the CP 110 slave and master dtsi by a following up patch. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-7040-db.dts | 2 ++ arch/arm64/boot/dts/marvell/armada-8040-db.dts | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts index 12442329b80f..771311051421 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts @@ -162,6 +162,8 @@ &cpm_sdhci0 { }; &cpm_mdio { + status = "okay"; + phy0: ethernet-phy@0 { reg = <0>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index 3cde649f96e4..6af3c39bbb99 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -125,6 +125,8 @@ &cpm_usb3_1 { }; &cpm_mdio { + status = "okay"; + phy1: ethernet-phy@1 { reg = <1>; }; @@ -170,6 +172,8 @@ &cps_usb3_1 { }; &cps_mdio { + status = "okay"; + phy0: ethernet-phy@0 { reg = <0>; }; From 5526bdc64141ab28784918533f8aee7f3fa7652d Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 8 Jun 2017 12:04:55 +0200 Subject: [PATCH 10/20] arm64: dts: marvell: disable the mdio nodes by default Disable the mdio nodes by default in the cp110 slave and master dtsi as they're not wired on every board. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index e02ac90f7fdf..571ce27de881 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -95,6 +95,7 @@ cpm_mdio: mdio@12a200 { compatible = "marvell,orion-mdio"; reg = <0x12a200 0x10>; clocks = <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>; + status = "disabled"; }; cpm_syscon0: system-controller@440000 { diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 7468fe00fc37..7e98c155cc6a 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -102,6 +102,7 @@ cps_mdio: mdio@12a200 { compatible = "marvell,orion-mdio"; reg = <0x12a200 0x10>; clocks = <&cps_syscon0 1 9>, <&cps_syscon0 1 5>; + status = "disabled"; }; cps_syscon0: system-controller@440000 { From 483b4da2bf1d62d2e71e1836bc0299cf2f3200dc Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 8 Jun 2017 12:56:23 +0200 Subject: [PATCH 11/20] arm64: dts: marvell: armada-3720-db: Sort the dts node alphabetically MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sort the reference nodes in alphabetical order to ease the merge of future nodes. Reviewed-by: Andreas Färber Signed-off-by: Gregory CLEMENT --- .../arm64/boot/dts/marvell/armada-3720-db.dts | 83 +++++++++---------- 1 file changed, 41 insertions(+), 42 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index a89855f57091..d6f12fafac6c 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -78,6 +78,20 @@ usb3_phy: usb3-phy { }; }; +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii-id"; + phy = <&phy0>; + status = "okay"; +}; + +ð1 { + phy-mode = "sgmii"; + phy = <&phy1>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -108,11 +122,36 @@ rtc@68 { }; }; +&mdio { + status = "okay"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +/* CON17 (PCIe) / CON12 (mini-PCIe) */ +&pcie0 { + status = "okay"; +}; + /* CON3 */ &sata { status = "okay"; }; +&sdhci0 { + non-removable; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + marvell,pad-type = "fixed-1-8v"; + status = "okay"; +}; + &spi0 { status = "okay"; pinctrl-names = "default"; @@ -152,12 +191,8 @@ &uart0 { status = "okay"; }; -&sdhci0 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,pad-type = "fixed-1-8v"; +/* CON27 */ +&usb2 { status = "okay"; }; @@ -166,39 +201,3 @@ &usb3 { status = "okay"; usb-phy = <&usb3_phy>; }; - -/* CON17 (PCIe) / CON12 (mini-PCIe) */ -&pcie0 { - status = "okay"; -}; - -/* CON27 */ -&usb2 { - status = "okay"; -}; - - -&mdio { - status = "okay"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii-id"; - phy = <&phy0>; - status = "okay"; -}; - -ð1 { - phy-mode = "sgmii"; - phy = <&phy1>; - status = "okay"; -}; From 718e46395c66959a88f2e450dad21cfb03ee4f48 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 8 Jun 2017 15:51:56 +0200 Subject: [PATCH 12/20] arm64: dts: marvell: armada-3720-db: Add information about the V2 board The initial device tree file was for the board V1.4. Now the V2.0 board is also available. The same dtb will work for both, but the CON number have changed, so update the comment in the dts to reflect this. Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-db.dts | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index d6f12fafac6c..3ee920ac0015 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -42,6 +42,10 @@ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. + * + * This file is compatible with the version 1.4 and the version 2.0 of + * the board, however the CON numbers are different between the 2 + * version */ /dts-v1/; @@ -78,6 +82,7 @@ usb3_phy: usb3-phy { }; }; +/* Gigabit module on CON19(V2.0)/CON21(V1.4) */ ð0 { pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; @@ -86,6 +91,7 @@ ð0 { status = "okay"; }; +/* Gigabit module on CON18(V2.0)/CON20(V1.4) */ ð1 { phy-mode = "sgmii"; phy = <&phy1>; @@ -133,7 +139,7 @@ phy1: ethernet-phy@1 { }; }; -/* CON17 (PCIe) / CON12 (mini-PCIe) */ +/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */ &pcie0 { status = "okay"; }; @@ -184,19 +190,22 @@ partition@210000 { }; }; -/* Exported on the micro USB connector CON32 through an FTDI */ +/* + * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through + * an FTDI + */ &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; status = "okay"; }; -/* CON27 */ +/* CON27(V2.0)/CON29(V1.4) */ &usb2 { status = "okay"; }; -/* CON31 */ +/* CON29(V2.0)/CON31(V1.4) */ &usb3 { status = "okay"; usb-phy = <&usb3_phy>; From 55ad5b1ae9745ed14715d832580d4551fefe2481 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 13 Jun 2017 12:34:03 +0200 Subject: [PATCH 13/20] arm64: dts: marvell: armada-37xx: Align the compatible string This cosmetic patch aligns the compatible string when there are on several lines. Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 4d495ec39202..c1076fd0bd9e 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -163,7 +163,7 @@ tbg: tbg@13200 { pinctrl_nb: pinctrl@13800 { compatible = "marvell,armada3710-nb-pinctrl", - "syscon", "simple-mfd"; + "syscon", "simple-mfd"; reg = <0x13800 0x100>, <0x13C00 0x20>; gpionb: gpio { #gpio-cells = <2>; @@ -219,7 +219,7 @@ uart2_pins: uart2-pins { pinctrl_sb: pinctrl@18800 { compatible = "marvell,armada3710-sb-pinctrl", - "syscon", "simple-mfd"; + "syscon", "simple-mfd"; reg = <0x18800 0x100>, <0x18C00 0x20>; gpiosb: gpio { #gpio-cells = <2>; @@ -294,7 +294,7 @@ xor11 { sdhci0: sdhci@d8000 { compatible = "marvell,armada-3700-sdhci", - "marvell,sdhci-xenon"; + "marvell,sdhci-xenon"; reg = <0xd8000 0x300 0x17808 0x4>; interrupts = ; From e9bfac543eaa01cdca7b810b9cd4eaf9e6a7f1b0 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 13 Jun 2017 14:25:46 +0200 Subject: [PATCH 14/20] arm64: dts: marvell: armada-37xx: Use angle bracket for each register set When several groups of register address and size are used with reg, then surround each one by angle bracket. Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index c1076fd0bd9e..65562319770b 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -281,8 +281,8 @@ usb2: usb@5e000 { xor@60900 { compatible = "marvell,armada-3700-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; + reg = <0x60900 0x100>, + <0x60b00 0x100>; xor10 { interrupts = ; @@ -295,8 +295,8 @@ xor11 { sdhci0: sdhci@d8000 { compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon"; - reg = <0xd8000 0x300 - 0x17808 0x4>; + reg = <0xd8000 0x300>, + <0x17808 0x4>; interrupts = ; clocks = <&nb_periph_clk 0>; clock-names = "core"; From 1208d2f0c84120d4e3eb2caf663a9a8b784b38ba Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Tue, 23 May 2017 16:11:40 +0300 Subject: [PATCH 15/20] arm64: dts: marvell: Enable second SDHCI controller in Armada 37xx The Armada 37xx SoCs has 2 SDHCI interfaces. This patch adds the second one. Moreover, the Armada 37xx DB v2 board populates the 2 SDHCI interfaces. The second interface is using pluggable module that can either have an SD connector or eMMC on it. This patch adds support for SD module in the device DT. [ gregory.clement@free-electrons.com: - Add more detail in commit log - Sort the dt node in address order - Document the SD slot in the dts ] Signed-off-by: Konstantin Porotchkin Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-db.dts | 9 +++++++++ arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index 3ee920ac0015..eab3bc7e6382 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -158,6 +158,15 @@ &sdhci0 { status = "okay"; }; +/* SD slot module on CON14(V2.0)/CON15(V1.4) */ +&sdhci1 { + wp-inverted; + cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; + bus-width = <4>; + marvell,pad-type = "sd"; + status = "okay"; +}; + &spi0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 65562319770b..b4d27857c61b 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -292,6 +292,17 @@ xor11 { }; }; + sdhci1: sdhci@d0000 { + compatible = "marvell,armada-3700-sdhci", + "marvell,sdhci-xenon"; + reg = <0xd0000 0x300>, + <0x1e808 0x4>; + interrupts = ; + clocks = <&nb_periph_clk 0>; + clock-names = "core"; + status = "disabled"; + }; + sdhci0: sdhci@d8000 { compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon"; From 07d065abf93dbced17d189f7c830467ca559c81d Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 8 Jun 2017 12:29:51 +0200 Subject: [PATCH 16/20] arm64: dts: marvell: armada-3720-db: Add vqmmc regulator for SD slot By adding this regulator, the SD cards are usable at higher speed protocols such as SDR104. This patch was tested with an SD HC card compatible with UHS-I. Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-db.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index eab3bc7e6382..9df0f06ce607 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -80,6 +80,20 @@ usb3_phy: usb3-phy { compatible = "usb-nop-xceiv"; vcc-supply = <&exp_usb3_vbus>; }; + + vcc_sd_reg1: regulator { + compatible = "regulator-gpio"; + regulator-name = "vcc_sd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1 + 3300000 0x0>; + enable-active-high; + }; }; /* Gigabit module on CON19(V2.0)/CON21(V1.4) */ @@ -164,6 +178,7 @@ &sdhci1 { cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; bus-width = <4>; marvell,pad-type = "sd"; + vqmmc-supply = <&vcc_sd_reg1>; status = "okay"; }; From bcd0256473af8d8efa107a6f8af34b63c50300f6 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 15 Jun 2017 14:10:02 +0200 Subject: [PATCH 17/20] arm64: dts: marvell: cp110: enable the crypto engine at the SoC level Enable the cryptographic engine at the SoC level on the master cp110. This engine is always present and do not depends on any pinmux configuration. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 571ce27de881..0a9edaa26a88 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -244,7 +244,6 @@ cpm_crypto: crypto@800000 { "ring2", "ring3", "eip"; clocks = <&cpm_syscon0 1 26>; dma-mask = <0xff 0xffffffff>; - status = "disabled"; }; }; From b97afaf69e6d47c69ef1448c9b1c431f0d2b5ea3 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 15 Jun 2017 14:10:03 +0200 Subject: [PATCH 18/20] arm64: dts: marvell: remove cpm crypto nodes from dts files The cryptographic engine on the master cp110 is now enabled by default at the SoC level. Remove its dts nodes that were only enabling it. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-7040-db.dts | 4 ---- arch/arm64/boot/dts/marvell/armada-8040-db.dts | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts index 771311051421..92c761c380d3 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts @@ -187,7 +187,3 @@ &cpm_eth2 { phy = <&phy1>; phy-mode = "rgmii-id"; }; - -&cpm_crypto { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index 6af3c39bbb99..1e8f7242ed6f 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -142,10 +142,6 @@ &cpm_eth2 { phy-mode = "rgmii-id"; }; -&cpm_crypto { - status = "okay"; -}; - /* CON5 on CP1 expansion */ &cps_pcie2 { status = "okay"; From c7c3d6731f7dd6c7a7b17179a8176584b0d795c2 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 15 Jun 2017 14:10:04 +0200 Subject: [PATCH 19/20] arm64: dts: marvell: add a comment on the cp110 slave node status The cryptographic engine found on the cp110 slave is disabled by default because of some known limitations. Add a comment to explain why it is disabled by default. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 7e98c155cc6a..385ac30d6012 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -234,6 +234,13 @@ cps_crypto: crypto@800000 { "ring2", "ring3", "eip"; clocks = <&cps_syscon0 1 26>; dma-mask = <0xff 0xffffffff>; + /* + * The cryptographic engine found on the cp110 + * master is enabled by default at the SoC + * level. Because it is not possible as of now + * to enable two cryptographic engines in + * parallel, disable this one by default. + */ status = "disabled"; }; }; From f66b2aff46eaf0825dbe1560e28fcb845dd2a215 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 15 Jun 2017 16:43:26 +0200 Subject: [PATCH 20/20] arm64: dts: marvell: add xmdio nodes for 7k/8k Add the description of the xMDIO bus for the Marvell Armada 7k and Marvell Armada 8k; for both CP110 slave and master. This bus is found on Marvell Ethernet controllers and provides an interface with the xMDIO bus. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 8 ++++++++ arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 0a9edaa26a88..d490a377d0c1 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -98,6 +98,14 @@ cpm_mdio: mdio@12a200 { status = "disabled"; }; + cpm_xmdio: mdio@12a600 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,xmdio"; + reg = <0x12a600 0x10>; + status = "disabled"; + }; + cpm_syscon0: system-controller@440000 { compatible = "marvell,cp110-system-controller0", "syscon"; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 385ac30d6012..dc4673dcf81b 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -105,6 +105,14 @@ cps_mdio: mdio@12a200 { status = "disabled"; }; + cps_xmdio: mdio@12a600 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,xmdio"; + reg = <0x12a600 0x10>; + status = "disabled"; + }; + cps_syscon0: system-controller@440000 { compatible = "marvell,cp110-system-controller0", "syscon";