mirror of https://gitee.com/openkylin/linux.git
Merge tag 'drm-intel-fixes-2014-08-28' of git://anongit.freedesktop.org/drm-intel into drm-fixes
Some more fixes for 3.17, mostly stable material. * tag 'drm-intel-fixes-2014-08-28' of git://anongit.freedesktop.org/drm-intel: drm/i915: Remove bogus __init annotation from DMI callbacks drm/i915: don't warn if backlight unexpectedly enabled drm/i915: Move intel_ddi_set_vc_payload_alloc(false) to haswell_crtc_disable() drm/i915: fix plane/cursor handling when runtime suspended drm/i915: Ignore VBT backlight presence check on Acer C720 (4005U)
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commit
46712cc959
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@ -1123,7 +1123,7 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
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}
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}
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static int __init intel_no_opregion_vbt_callback(const struct dmi_system_id *id)
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static int intel_no_opregion_vbt_callback(const struct dmi_system_id *id)
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{
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DRM_DEBUG_KMS("Falling back to manually reading VBT from "
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"VBIOS ROM for %s\n",
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@ -804,7 +804,7 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = {
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.destroy = intel_encoder_destroy,
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};
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static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
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static int intel_no_crt_dmi_callback(const struct dmi_system_id *id)
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{
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DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
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return 1;
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@ -2233,6 +2233,15 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
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if (need_vtd_wa(dev) && alignment < 256 * 1024)
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alignment = 256 * 1024;
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/*
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* Global gtt pte registers are special registers which actually forward
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* writes to a chunk of system memory. Which means that there is no risk
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* that the register values disappear as soon as we call
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* intel_runtime_pm_put(), so it is correct to wrap only the
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* pin/unpin/fence and not more.
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*/
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intel_runtime_pm_get(dev_priv);
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dev_priv->mm.interruptible = false;
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ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
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if (ret)
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@ -2250,12 +2259,14 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
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i915_gem_object_pin_fence(obj);
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dev_priv->mm.interruptible = true;
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intel_runtime_pm_put(dev_priv);
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return 0;
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err_unpin:
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i915_gem_object_unpin_from_display_plane(obj);
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err_interruptible:
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dev_priv->mm.interruptible = true;
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intel_runtime_pm_put(dev_priv);
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return ret;
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}
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@ -4188,10 +4199,6 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
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intel_disable_pipe(dev_priv, pipe);
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if (intel_crtc->config.dp_encoder_is_mst)
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intel_ddi_set_vc_payload_alloc(crtc, false);
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ironlake_pfit_disable(intel_crtc);
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for_each_encoder_on_crtc(dev, crtc, encoder)
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@ -4256,6 +4263,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
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intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
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intel_disable_pipe(dev_priv, pipe);
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if (intel_crtc->config.dp_encoder_is_mst)
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intel_ddi_set_vc_payload_alloc(crtc, false);
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intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
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ironlake_pfit_disable(intel_crtc);
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@ -8240,6 +8250,15 @@ static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
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goto fail_locked;
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}
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/*
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* Global gtt pte registers are special registers which actually
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* forward writes to a chunk of system memory. Which means that
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* there is no risk that the register values disappear as soon
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* as we call intel_runtime_pm_put(), so it is correct to wrap
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* only the pin/unpin/fence and not more.
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*/
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intel_runtime_pm_get(dev_priv);
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/* Note that the w/a also requires 2 PTE of padding following
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* the bo. We currently fill all unused PTE with the shadow
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* page and so we should always have valid PTE following the
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@ -8252,16 +8271,20 @@ static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
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ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
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if (ret) {
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DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
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intel_runtime_pm_put(dev_priv);
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goto fail_locked;
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}
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ret = i915_gem_object_put_fence(obj);
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if (ret) {
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DRM_DEBUG_KMS("failed to release fence for cursor");
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intel_runtime_pm_put(dev_priv);
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goto fail_unpin;
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}
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addr = i915_gem_obj_ggtt_offset(obj);
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intel_runtime_pm_put(dev_priv);
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} else {
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int align = IS_I830(dev) ? 16 * 1024 : 256;
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ret = i915_gem_object_attach_phys(obj, align);
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@ -12481,6 +12504,9 @@ static struct intel_quirk intel_quirks[] = {
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/* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
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{ 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
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/* Acer C720 Chromebook (Core i3 4005U) */
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{ 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
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/* Toshiba CB35 Chromebook (Celeron 2955U) */
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{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
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@ -538,7 +538,7 @@ static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
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.destroy = intel_encoder_destroy,
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};
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static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
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static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
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{
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DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
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return 1;
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@ -801,7 +801,7 @@ static void pch_enable_backlight(struct intel_connector *connector)
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cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
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if (cpu_ctl2 & BLM_PWM_ENABLE) {
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WARN(1, "cpu backlight already enabled\n");
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DRM_DEBUG_KMS("cpu backlight already enabled\n");
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cpu_ctl2 &= ~BLM_PWM_ENABLE;
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I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2);
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}
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@ -845,7 +845,7 @@ static void i9xx_enable_backlight(struct intel_connector *connector)
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ctl = I915_READ(BLC_PWM_CTL);
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if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) {
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WARN(1, "backlight already enabled\n");
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DRM_DEBUG_KMS("backlight already enabled\n");
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I915_WRITE(BLC_PWM_CTL, 0);
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}
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@ -876,7 +876,7 @@ static void i965_enable_backlight(struct intel_connector *connector)
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ctl2 = I915_READ(BLC_PWM_CTL2);
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if (ctl2 & BLM_PWM_ENABLE) {
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WARN(1, "backlight already enabled\n");
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DRM_DEBUG_KMS("backlight already enabled\n");
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ctl2 &= ~BLM_PWM_ENABLE;
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I915_WRITE(BLC_PWM_CTL2, ctl2);
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}
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@ -910,7 +910,7 @@ static void vlv_enable_backlight(struct intel_connector *connector)
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ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
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if (ctl2 & BLM_PWM_ENABLE) {
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WARN(1, "backlight already enabled\n");
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DRM_DEBUG_KMS("backlight already enabled\n");
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ctl2 &= ~BLM_PWM_ENABLE;
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I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2);
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}
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