mirror of https://gitee.com/openkylin/linux.git
perf/x86/intel: Fix SNB-EP CBO and PCU uncore PMU filter management
The existing code assumes all Cbox and PCU events are using filter, but actually the filter is event specific. Furthermore the filter is sub-divided into multiple fields which are used by different events. Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: peterz@infradead.org Cc: ak@linux.intel.com Link: http://lkml.kernel.org/r/1366113067-3262-3-git-send-email-zheng.z.yan@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org> Reported-by: Stephane Eranian <eranian@google.com>
This commit is contained in:
Yan, Zheng
Ingo Molnar
parent
22cc4ccf63
commit
46bdd90598
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@ -17,6 +17,9 @@ static struct event_constraint constraint_fixed =
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static struct event_constraint constraint_empty =
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EVENT_CONSTRAINT(0, 0, 0);
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#define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \
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((1ULL << (n)) - 1)))
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DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
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DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
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DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
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@ -110,6 +113,21 @@ static void uncore_put_constraint(struct intel_uncore_box *box, struct perf_even
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reg1->alloc = 0;
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}
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static u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx)
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{
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struct intel_uncore_extra_reg *er;
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unsigned long flags;
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u64 config;
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er = &box->shared_regs[idx];
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raw_spin_lock_irqsave(&er->lock, flags);
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config = er->config;
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raw_spin_unlock_irqrestore(&er->lock, flags);
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return config;
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}
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/* Sandy Bridge-EP uncore support */
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static struct intel_uncore_type snbep_uncore_cbox;
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static struct intel_uncore_type snbep_uncore_pcu;
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@ -205,7 +223,7 @@ static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct p
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struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
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if (reg1->idx != EXTRA_REG_NONE)
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wrmsrl(reg1->reg, reg1->config);
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wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0));
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wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
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}
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@ -226,29 +244,6 @@ static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
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wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
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}
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static int snbep_uncore_hw_config(struct intel_uncore_box *box, struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
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if (box->pmu->type == &snbep_uncore_cbox) {
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reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
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SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
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reg1->config = event->attr.config1 &
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SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK;
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} else {
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if (box->pmu->type == &snbep_uncore_pcu) {
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reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
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reg1->config = event->attr.config1 & SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK;
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} else {
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return 0;
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}
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}
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reg1->idx = 0;
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return 0;
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}
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static struct attribute *snbep_uncore_formats_attr[] = {
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&format_attr_event.attr,
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&format_attr_umask.attr,
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@ -345,16 +340,16 @@ static struct attribute_group snbep_uncore_qpi_format_group = {
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.attrs = snbep_uncore_qpi_formats_attr,
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};
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#define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
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.init_box = snbep_uncore_msr_init_box, \
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.disable_box = snbep_uncore_msr_disable_box, \
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.enable_box = snbep_uncore_msr_enable_box, \
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.disable_event = snbep_uncore_msr_disable_event, \
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.enable_event = snbep_uncore_msr_enable_event, \
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.read_counter = uncore_msr_read_counter
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static struct intel_uncore_ops snbep_uncore_msr_ops = {
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.init_box = snbep_uncore_msr_init_box,
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.disable_box = snbep_uncore_msr_disable_box,
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.enable_box = snbep_uncore_msr_enable_box,
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.disable_event = snbep_uncore_msr_disable_event,
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.enable_event = snbep_uncore_msr_enable_event,
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.read_counter = uncore_msr_read_counter,
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.get_constraint = uncore_get_constraint,
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.put_constraint = uncore_put_constraint,
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.hw_config = snbep_uncore_hw_config,
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SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
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};
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static struct intel_uncore_ops snbep_uncore_pci_ops = {
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@ -446,6 +441,145 @@ static struct intel_uncore_type snbep_uncore_ubox = {
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.format_group = &snbep_uncore_ubox_format_group,
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};
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static struct extra_reg snbep_uncore_cbox_extra_regs[] = {
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SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
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SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
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SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
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SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
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SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
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SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6),
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SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8),
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SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8),
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SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0xc),
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SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0xc),
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SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x2),
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SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x2),
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SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x2),
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SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x2),
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SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x8),
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SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x8),
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SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0xc),
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SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0xc),
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SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x2),
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SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x2),
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SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x2),
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SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x2),
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EVENT_EXTRA_END
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};
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static void snbep_cbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
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{
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struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
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struct intel_uncore_extra_reg *er = &box->shared_regs[0];
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int i;
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if (uncore_box_is_fake(box))
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return;
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for (i = 0; i < 5; i++) {
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if (reg1->alloc & (0x1 << i))
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atomic_sub(1 << (i * 6), &er->ref);
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}
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reg1->alloc = 0;
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}
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static struct event_constraint *
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__snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event,
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u64 (*cbox_filter_mask)(int fields))
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{
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struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
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struct intel_uncore_extra_reg *er = &box->shared_regs[0];
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int i, alloc = 0;
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unsigned long flags;
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u64 mask;
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if (reg1->idx == EXTRA_REG_NONE)
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return NULL;
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raw_spin_lock_irqsave(&er->lock, flags);
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for (i = 0; i < 5; i++) {
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if (!(reg1->idx & (0x1 << i)))
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continue;
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if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
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continue;
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mask = cbox_filter_mask(0x1 << i);
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if (!__BITS_VALUE(atomic_read(&er->ref), i, 6) ||
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!((reg1->config ^ er->config) & mask)) {
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atomic_add(1 << (i * 6), &er->ref);
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er->config &= ~mask;
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er->config |= reg1->config & mask;
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alloc |= (0x1 << i);
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} else {
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break;
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}
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}
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raw_spin_unlock_irqrestore(&er->lock, flags);
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if (i < 5)
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goto fail;
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if (!uncore_box_is_fake(box))
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reg1->alloc |= alloc;
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return 0;
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fail:
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for (; i >= 0; i--) {
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if (alloc & (0x1 << i))
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atomic_sub(1 << (i * 6), &er->ref);
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}
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return &constraint_empty;
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}
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static u64 snbep_cbox_filter_mask(int fields)
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{
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u64 mask = 0;
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if (fields & 0x1)
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mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_TID;
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if (fields & 0x2)
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mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_NID;
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if (fields & 0x4)
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mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE;
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if (fields & 0x8)
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mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC;
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return mask;
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}
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static struct event_constraint *
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snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
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{
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return __snbep_cbox_get_constraint(box, event, snbep_cbox_filter_mask);
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}
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static int snbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
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{
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struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
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struct extra_reg *er;
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int idx = 0;
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for (er = snbep_uncore_cbox_extra_regs; er->msr; er++) {
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if (er->event != (event->hw.config & er->config_mask))
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continue;
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idx |= er->idx;
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}
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if (idx) {
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reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
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SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
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reg1->config = event->attr.config1 & snbep_cbox_filter_mask(idx);
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reg1->idx = idx;
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}
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return 0;
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}
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static struct intel_uncore_ops snbep_uncore_cbox_ops = {
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SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
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.hw_config = snbep_cbox_hw_config,
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.get_constraint = snbep_cbox_get_constraint,
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.put_constraint = snbep_cbox_put_constraint,
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};
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static struct intel_uncore_type snbep_uncore_cbox = {
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.name = "cbox",
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.num_counters = 4,
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@ -458,10 +592,104 @@ static struct intel_uncore_type snbep_uncore_cbox = {
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.msr_offset = SNBEP_CBO_MSR_OFFSET,
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.num_shared_regs = 1,
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.constraints = snbep_uncore_cbox_constraints,
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.ops = &snbep_uncore_msr_ops,
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.ops = &snbep_uncore_cbox_ops,
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.format_group = &snbep_uncore_cbox_format_group,
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};
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static u64 snbep_pcu_alter_er(struct perf_event *event, int new_idx, bool modify)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
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u64 config = reg1->config;
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if (new_idx > reg1->idx)
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config <<= 8 * (new_idx - reg1->idx);
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else
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config >>= 8 * (reg1->idx - new_idx);
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if (modify) {
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hwc->config += new_idx - reg1->idx;
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reg1->config = config;
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reg1->idx = new_idx;
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}
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return config;
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}
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static struct event_constraint *
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snbep_pcu_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
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{
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struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
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struct intel_uncore_extra_reg *er = &box->shared_regs[0];
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unsigned long flags;
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int idx = reg1->idx;
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u64 mask, config1 = reg1->config;
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bool ok = false;
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if (reg1->idx == EXTRA_REG_NONE ||
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(!uncore_box_is_fake(box) && reg1->alloc))
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return NULL;
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again:
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mask = 0xff << (idx * 8);
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raw_spin_lock_irqsave(&er->lock, flags);
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if (!__BITS_VALUE(atomic_read(&er->ref), idx, 8) ||
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!((config1 ^ er->config) & mask)) {
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atomic_add(1 << (idx * 8), &er->ref);
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er->config &= ~mask;
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er->config |= config1 & mask;
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ok = true;
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}
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raw_spin_unlock_irqrestore(&er->lock, flags);
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if (!ok) {
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idx = (idx + 1) % 4;
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if (idx != reg1->idx) {
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config1 = snbep_pcu_alter_er(event, idx, false);
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goto again;
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}
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return &constraint_empty;
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}
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if (!uncore_box_is_fake(box)) {
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if (idx != reg1->idx)
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snbep_pcu_alter_er(event, idx, true);
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reg1->alloc = 1;
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}
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return NULL;
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}
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static void snbep_pcu_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
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{
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struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
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struct intel_uncore_extra_reg *er = &box->shared_regs[0];
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if (uncore_box_is_fake(box) || !reg1->alloc)
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return;
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atomic_sub(1 << (reg1->idx * 8), &er->ref);
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reg1->alloc = 0;
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}
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static int snbep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
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int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK;
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if (ev_sel >= 0xb && ev_sel <= 0xe) {
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reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
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reg1->idx = ev_sel - 0xb;
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reg1->config = event->attr.config1 & (0xff << reg1->idx);
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}
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return 0;
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}
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static struct intel_uncore_ops snbep_uncore_pcu_ops = {
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SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
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.hw_config = snbep_pcu_hw_config,
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.get_constraint = snbep_pcu_get_constraint,
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.put_constraint = snbep_pcu_put_constraint,
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};
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static struct intel_uncore_type snbep_uncore_pcu = {
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.name = "pcu",
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.num_counters = 4,
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@ -472,7 +700,7 @@ static struct intel_uncore_type snbep_uncore_pcu = {
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.event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
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.box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
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.num_shared_regs = 1,
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.ops = &snbep_uncore_msr_ops,
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.ops = &snbep_uncore_pcu_ops,
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.format_group = &snbep_uncore_pcu_format_group,
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};
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@ -808,9 +1036,6 @@ static struct intel_uncore_type *nhm_msr_uncores[] = {
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/* end of Nehalem uncore support */
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/* Nehalem-EX uncore support */
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#define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \
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((1ULL << (n)) - 1)))
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DEFINE_UNCORE_FORMAT_ATTR(event5, event, "config:1-5");
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DEFINE_UNCORE_FORMAT_ATTR(counter, counter, "config:6-7");
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DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63");
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@ -1161,7 +1386,7 @@ static struct extra_reg nhmex_uncore_mbox_extra_regs[] = {
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};
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/* Nehalem-EX or Westmere-EX ? */
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bool uncore_nhmex;
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static bool uncore_nhmex;
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static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64 config)
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{
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@ -1239,7 +1464,7 @@ static void nhmex_mbox_put_shared_reg(struct intel_uncore_box *box, int idx)
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atomic_sub(1 << (idx * 8), &er->ref);
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}
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u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify)
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static u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify)
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{
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struct hw_perf_event *hwc = &event->hw;
|
||||
struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
|
||||
|
|
@ -1554,7 +1779,7 @@ static struct intel_uncore_type nhmex_uncore_mbox = {
|
|||
.format_group = &nhmex_uncore_mbox_format_group,
|
||||
};
|
||||
|
||||
void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
|
||||
static void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
|
||||
|
|
@ -1724,21 +1949,6 @@ static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event
|
|||
return 0;
|
||||
}
|
||||
|
||||
static u64 nhmex_rbox_shared_reg_config(struct intel_uncore_box *box, int idx)
|
||||
{
|
||||
struct intel_uncore_extra_reg *er;
|
||||
unsigned long flags;
|
||||
u64 config;
|
||||
|
||||
er = &box->shared_regs[idx];
|
||||
|
||||
raw_spin_lock_irqsave(&er->lock, flags);
|
||||
config = er->config;
|
||||
raw_spin_unlock_irqrestore(&er->lock, flags);
|
||||
|
||||
return config;
|
||||
}
|
||||
|
||||
static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
|
|
@ -1759,7 +1969,7 @@ static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct per
|
|||
case 2:
|
||||
case 3:
|
||||
wrmsrl(NHMEX_R_MSR_PORTN_QLX_CFG(port),
|
||||
nhmex_rbox_shared_reg_config(box, 2 + (idx / 6) * 5));
|
||||
uncore_shared_reg_config(box, 2 + (idx / 6) * 5));
|
||||
break;
|
||||
case 4:
|
||||
wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port),
|
||||
|
|
@ -2285,7 +2495,7 @@ static int uncore_validate_group(struct intel_uncore_pmu *pmu,
|
|||
return ret;
|
||||
}
|
||||
|
||||
int uncore_pmu_event_init(struct perf_event *event)
|
||||
static int uncore_pmu_event_init(struct perf_event *event)
|
||||
{
|
||||
struct intel_uncore_pmu *pmu;
|
||||
struct intel_uncore_box *box;
|
||||
|
|
|
|||
|
|
@ -148,9 +148,20 @@
|
|||
#define SNBEP_C0_MSR_PMON_CTL0 0xd10
|
||||
#define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04
|
||||
#define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14
|
||||
#define SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK 0xfffffc1f
|
||||
#define SNBEP_CBO_MSR_OFFSET 0x20
|
||||
|
||||
#define SNBEP_CB0_MSR_PMON_BOX_FILTER_TID 0x1f
|
||||
#define SNBEP_CB0_MSR_PMON_BOX_FILTER_NID 0x3fc00
|
||||
#define SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE 0x7c0000
|
||||
#define SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC 0xff800000
|
||||
|
||||
#define SNBEP_CBO_EVENT_EXTRA_REG(e, m, i) { \
|
||||
.event = (e), \
|
||||
.msr = SNBEP_C0_MSR_PMON_BOX_FILTER, \
|
||||
.config_mask = (m), \
|
||||
.idx = (i) \
|
||||
}
|
||||
|
||||
/* SNB-EP PCU register */
|
||||
#define SNBEP_PCU_MSR_PMON_CTR0 0xc36
|
||||
#define SNBEP_PCU_MSR_PMON_CTL0 0xc30
|
||||
|
|
|
|||
Loading…
Reference in New Issue