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ARM: 6416/1: errata: faulty hazard checking in the Store Buffer may lead to data corruption
On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption can occur under very rare conditions due to a store buffer optimisation. This workaround sets a bit in the diagnostic register of the Cortex-A9, disabling the optimisation and preventing the problem from occurring. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -1101,6 +1101,20 @@ config ARM_ERRATA_720789
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invalidated are not, resulting in an incoherency in the system page
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invalidated are not, resulting in an incoherency in the system page
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tables. The workaround changes the TLB flushing routines to invalidate
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tables. The workaround changes the TLB flushing routines to invalidate
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entries regardless of the ASID.
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entries regardless of the ASID.
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config ARM_ERRATA_743622
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bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
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depends on CPU_V7
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help
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This option enables the workaround for the 743622 Cortex-A9
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(r2p0..r2p2) erratum. Under very rare conditions, a faulty
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optimisation in the Cortex-A9 Store Buffer may lead to data
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corruption. This workaround sets a specific bit in the diagnostic
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register of the Cortex-A9 which disables the Store Buffer
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optimisation, preventing the defect from occurring. This has no
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visible impact on the overall performance or power consumption of the
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processor.
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endmenu
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endmenu
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source "arch/arm/common/Kconfig"
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source "arch/arm/common/Kconfig"
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@ -253,6 +253,14 @@ __v7_setup:
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orreq r10, r10, #1 << 22 @ set bit #22
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orreq r10, r10, #1 << 22 @ set bit #22
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mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
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mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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#endif
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#ifdef CONFIG_ARM_ERRATA_743622
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teq r6, #0x20 @ present in r2p0
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teqne r6, #0x21 @ present in r2p1
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teqne r6, #0x22 @ present in r2p2
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mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orreq r10, r10, #1 << 6 @ set bit #6
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mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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3: mov r10, #0
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3: mov r10, #0
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#ifdef HARVARD_CACHE
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#ifdef HARVARD_CACHE
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