mirror of https://gitee.com/openkylin/linux.git
Merge branch 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar: - new driver for Broadcom FlexRM controller - constify data structures of callback functions in some drivers - a few bug fixes uncovered by multi-threaded use of mailbox channels in blocking mode * 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: handle empty message in tx_tick mailbox: skip complete wait event if timer expired mailbox: always wait in mbox_send_message for blocking Tx mode mailbox: Remove depends on COMPILE_TEST for BCM_FLEXRM_MBOX mailbox: check ->last_tx_done for NULL in case of timer-based polling dt-bindings: Add DT bindings info for FlexRM ring manager mailbox: Add driver for Broadcom FlexRM ring manager dt-bindings: mailbox: Update doc with NSP PDC/mailbox support mailbox: bcm-pdc: Add Northstar Plus support to PDC driver mailbox: constify mbox_chan_ops structures
This commit is contained in:
Linus Torvalds
commit
477d7caeed
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@ -0,0 +1,59 @@
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Broadcom FlexRM Ring Manager
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============================
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The Broadcom FlexRM ring manager provides a set of rings which can be
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used to submit work to offload engines. An SoC may have multiple FlexRM
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hardware blocks. There is one device tree entry per FlexRM block. The
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FlexRM driver will create a mailbox-controller instance for given FlexRM
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hardware block where each mailbox channel is a separate FlexRM ring.
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Required properties:
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--------------------
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- compatible: Should be "brcm,iproc-flexrm-mbox"
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- reg: Specifies base physical address and size of the FlexRM
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ring registers
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- msi-parent: Phandles (and potential Device IDs) to MSI controllers
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The FlexRM engine will send MSIs (instead of wired
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interrupts) to CPU. There is one MSI for each FlexRM ring.
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Refer devicetree/bindings/interrupt-controller/msi.txt
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- #mbox-cells: Specifies the number of cells needed to encode a mailbox
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channel. This should be 3.
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The 1st cell is the mailbox channel number.
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The 2nd cell contains MSI completion threshold. This is the
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number of completion messages for which FlexRM will inject
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one MSI interrupt to CPU.
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The 3nd cell contains MSI timer value representing time for
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which FlexRM will wait to accumulate N completion messages
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where N is the value specified by 2nd cell above. If FlexRM
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does not get required number of completion messages in time
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specified by this cell then it will inject one MSI interrupt
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to CPU provided atleast one completion message is available.
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Optional properties:
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--------------------
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- dma-coherent: Present if DMA operations made by the FlexRM engine (such
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as DMA descriptor access, access to buffers pointed by DMA
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descriptors and read/write pointer updates to DDR) are
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cache coherent with the CPU.
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Example:
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--------
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crypto_mbox: mbox@67000000 {
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compatible = "brcm,iproc-flexrm-mbox";
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reg = <0x67000000 0x200000>;
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msi-parent = <&gic_its 0x7f00>;
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#mbox-cells = <3>;
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};
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crypto@672c0000 {
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compatible = "brcm,spu2-v2-crypto";
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reg = <0x672c0000 0x1000>;
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mboxes = <&crypto_mbox 0 0x1 0xffff>,
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<&crypto_mbox 1 0x1 0xffff>,
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<&crypto_mbox 16 0x1 0xffff>,
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<&crypto_mbox 17 0x1 0xffff>,
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<&crypto_mbox 30 0x1 0xffff>,
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<&crypto_mbox 31 0x1 0xffff>;
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};
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@ -1,9 +1,11 @@
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The PDC driver manages data transfer to and from various offload engines
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on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is
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one device tree entry per block.
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one device tree entry per block. On some chips, the PDC functionality is
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handled by the FA2 (Northstar Plus).
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Required properties:
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- compatible : Should be "brcm,iproc-pdc-mbox".
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- compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for
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FA2/Northstar Plus.
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- reg: Should contain PDC registers location and length.
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- interrupts: Should contain the IRQ line for the PDC.
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- #mbox-cells: 1
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@ -144,12 +144,22 @@ config XGENE_SLIMPRO_MBOX
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want to use the APM X-Gene SLIMpro IPCM support.
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config BCM_PDC_MBOX
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tristate "Broadcom PDC Mailbox"
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depends on ARM64 || COMPILE_TEST
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tristate "Broadcom FlexSparx DMA Mailbox"
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depends on ARCH_BCM_IPROC || COMPILE_TEST
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depends on HAS_DMA
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help
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Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
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which provides access to various offload engines on Broadcom
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SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
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config BCM_FLEXRM_MBOX
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tristate "Broadcom FlexRM Mailbox"
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depends on ARM64
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depends on HAS_DMA
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select GENERIC_MSI_IRQ_DOMAIN
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default ARCH_BCM_IPROC
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help
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Mailbox implementation for the Broadcom PDC ring manager,
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Mailbox implementation of the Broadcom FlexRM ring manager,
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which provides access to various offload engines on Broadcom
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SoCs. Say Y here if you want to use the Broadcom PDC.
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SoCs. Say Y here if you want to use the Broadcom FlexRM.
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endif
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@ -30,4 +30,6 @@ obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o
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obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o
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obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o
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obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
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File diff suppressed because it is too large
Load Diff
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@ -18,7 +18,8 @@
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* Broadcom PDC Mailbox Driver
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* The PDC provides a ring based programming interface to one or more hardware
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* offload engines. For example, the PDC driver works with both SPU-M and SPU2
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* cryptographic offload hardware. In some chips the PDC is referred to as MDE.
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* cryptographic offload hardware. In some chips the PDC is referred to as MDE,
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* and in others the FA2/FA+ hardware is used with this PDC driver.
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*
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* The PDC driver registers with the Linux mailbox framework as a mailbox
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* controller, once for each PDC instance. Ring 0 for each PDC is registered as
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@ -108,6 +109,7 @@
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#define PDC_INTMASK_OFFSET 0x24
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#define PDC_INTSTATUS_OFFSET 0x20
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#define PDC_RCVLAZY0_OFFSET (0x30 + 4 * PDC_RINGSET)
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#define FA_RCVLAZY0_OFFSET 0x100
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/*
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* For SPU2, configure MDE_CKSUM_CONTROL to write 17 bytes of metadata
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@ -162,6 +164,11 @@
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/* Maximum size buffer the DMA engine can handle */
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#define PDC_DMA_BUF_MAX 16384
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enum pdc_hw {
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FA_HW, /* FA2/FA+ hardware (i.e. Northstar Plus) */
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PDC_HW /* PDC/MDE hardware (i.e. Northstar 2, Pegasus) */
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};
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struct pdc_dma_map {
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void *ctx; /* opaque context associated with frame */
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};
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@ -211,13 +218,13 @@ struct pdc_regs {
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u32 gptimer; /* 0x028 */
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u32 PAD;
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u32 intrcvlazy_0; /* 0x030 */
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u32 intrcvlazy_1; /* 0x034 */
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u32 intrcvlazy_2; /* 0x038 */
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u32 intrcvlazy_3; /* 0x03c */
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u32 intrcvlazy_0; /* 0x030 (Only in PDC, not FA2) */
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u32 intrcvlazy_1; /* 0x034 (Only in PDC, not FA2) */
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u32 intrcvlazy_2; /* 0x038 (Only in PDC, not FA2) */
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u32 intrcvlazy_3; /* 0x03c (Only in PDC, not FA2) */
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u32 PAD[48];
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u32 removed_intrecvlazy; /* 0x100 */
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u32 fa_intrecvlazy; /* 0x100 (Only in FA2, not PDC) */
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u32 flowctlthresh; /* 0x104 */
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u32 wrrthresh; /* 0x108 */
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u32 gmac_idle_cnt_thresh; /* 0x10c */
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@ -243,7 +250,7 @@ struct pdc_regs {
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u32 serdes_status1; /* 0x1b0 */
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u32 PAD[11]; /* 0x1b4-1dc */
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u32 clk_ctl_st; /* 0x1e0 */
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u32 hw_war; /* 0x1e4 */
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u32 hw_war; /* 0x1e4 (Only in PDC, not FA2) */
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u32 pwrctl; /* 0x1e8 */
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u32 PAD[5];
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@ -410,6 +417,9 @@ struct pdc_state {
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u32 txnobuf; /* unable to create tx descriptor */
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u32 rxnobuf; /* unable to create rx descriptor */
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u32 rx_oflow; /* count of rx overflows */
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/* hardware type - FA2 or PDC/MDE */
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enum pdc_hw hw_type;
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};
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/* Global variables */
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@ -1396,7 +1406,13 @@ static int pdc_interrupts_init(struct pdc_state *pdcs)
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/* interrupt configuration */
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iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);
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iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase + PDC_RCVLAZY0_OFFSET);
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if (pdcs->hw_type == FA_HW)
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iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase +
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FA_RCVLAZY0_OFFSET);
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else
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iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase +
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PDC_RCVLAZY0_OFFSET);
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/* read irq from device tree */
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pdcs->pdc_irq = irq_of_parse_and_map(dn, 0);
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@ -1465,6 +1481,17 @@ static int pdc_mb_init(struct pdc_state *pdcs)
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return 0;
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}
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/* Device tree API */
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static const int pdc_hw = PDC_HW;
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static const int fa_hw = FA_HW;
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static const struct of_device_id pdc_mbox_of_match[] = {
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{.compatible = "brcm,iproc-pdc-mbox", .data = &pdc_hw},
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{.compatible = "brcm,iproc-fa2-mbox", .data = &fa_hw},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, pdc_mbox_of_match);
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/**
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* pdc_dt_read() - Read application-specific data from device tree.
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* @pdev: Platform device
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@ -1481,6 +1508,8 @@ static int pdc_dt_read(struct platform_device *pdev, struct pdc_state *pdcs)
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{
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struct device *dev = &pdev->dev;
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struct device_node *dn = pdev->dev.of_node;
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const struct of_device_id *match;
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const int *hw_type;
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int err;
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err = of_property_read_u32(dn, "brcm,rx-status-len",
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@ -1492,6 +1521,14 @@ static int pdc_dt_read(struct platform_device *pdev, struct pdc_state *pdcs)
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pdcs->use_bcm_hdr = of_property_read_bool(dn, "brcm,use-bcm-hdr");
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pdcs->hw_type = PDC_HW;
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match = of_match_device(of_match_ptr(pdc_mbox_of_match), dev);
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if (match != NULL) {
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hw_type = match->data;
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pdcs->hw_type = *hw_type;
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}
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return 0;
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}
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@ -1525,7 +1562,7 @@ static int pdc_probe(struct platform_device *pdev)
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pdcs->pdc_idx = pdcg.num_spu;
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pdcg.num_spu++;
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err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
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err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(39));
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if (err) {
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dev_warn(dev, "PDC device cannot perform DMA. Error %d.", err);
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goto cleanup;
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@ -1611,12 +1648,6 @@ static int pdc_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id pdc_mbox_of_match[] = {
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{.compatible = "brcm,iproc-pdc-mbox"},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, pdc_mbox_of_match);
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static struct platform_driver pdc_mbox_driver = {
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.probe = pdc_probe,
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.remove = pdc_remove,
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@ -221,7 +221,7 @@ static void hi6220_mbox_shutdown(struct mbox_chan *chan)
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mbox->irq_map_chan[mchan->ack_irq] = NULL;
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}
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static struct mbox_chan_ops hi6220_mbox_ops = {
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static const struct mbox_chan_ops hi6220_mbox_ops = {
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.send_data = hi6220_mbox_send_data,
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.startup = hi6220_mbox_startup,
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.shutdown = hi6220_mbox_shutdown,
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@ -174,7 +174,7 @@ static void slimpro_mbox_shutdown(struct mbox_chan *chan)
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devm_free_irq(mb_chan->dev, mb_chan->irq, mb_chan);
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}
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static struct mbox_chan_ops slimpro_mbox_ops = {
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static const struct mbox_chan_ops slimpro_mbox_ops = {
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.send_data = slimpro_mbox_send_data,
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.startup = slimpro_mbox_startup,
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.shutdown = slimpro_mbox_shutdown,
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@ -103,11 +103,14 @@ static void tx_tick(struct mbox_chan *chan, int r)
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/* Submit next message */
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msg_submit(chan);
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if (!mssg)
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return;
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/* Notify the client */
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if (mssg && chan->cl->tx_done)
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if (chan->cl->tx_done)
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chan->cl->tx_done(chan->cl, mssg, r);
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if (chan->cl->tx_block)
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if (r != -ETIME && chan->cl->tx_block)
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complete(&chan->tx_complete);
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}
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@ -260,7 +263,7 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg)
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msg_submit(chan);
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if (chan->cl->tx_block && chan->active_req) {
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if (chan->cl->tx_block) {
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unsigned long wait;
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int ret;
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@ -271,8 +274,8 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg)
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ret = wait_for_completion_timeout(&chan->tx_complete, wait);
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if (ret == 0) {
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t = -EIO;
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tx_tick(chan, -EIO);
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t = -ETIME;
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tx_tick(chan, t);
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}
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}
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@ -453,6 +456,12 @@ int mbox_controller_register(struct mbox_controller *mbox)
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txdone = TXDONE_BY_ACK;
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if (txdone == TXDONE_BY_POLL) {
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if (!mbox->ops->last_tx_done) {
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dev_err(mbox->dev, "last_tx_done method is absent\n");
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return -EINVAL;
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}
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hrtimer_init(&mbox->poll_hrt, CLOCK_MONOTONIC,
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HRTIMER_MODE_REL);
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mbox->poll_hrt.function = txdone_hrtimer;
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@ -16,6 +16,7 @@
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enum brcm_message_type {
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BRCM_MESSAGE_UNKNOWN = 0,
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BRCM_MESSAGE_BATCH,
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BRCM_MESSAGE_SPU,
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BRCM_MESSAGE_SBA,
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BRCM_MESSAGE_MAX,
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@ -23,23 +24,28 @@ enum brcm_message_type {
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struct brcm_sba_command {
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u64 cmd;
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u64 *cmd_dma;
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dma_addr_t cmd_dma_addr;
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#define BRCM_SBA_CMD_TYPE_A BIT(0)
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#define BRCM_SBA_CMD_TYPE_B BIT(1)
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#define BRCM_SBA_CMD_TYPE_C BIT(2)
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#define BRCM_SBA_CMD_HAS_RESP BIT(3)
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#define BRCM_SBA_CMD_HAS_OUTPUT BIT(4)
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u64 flags;
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dma_addr_t input;
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size_t input_len;
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dma_addr_t resp;
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size_t resp_len;
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||||
dma_addr_t output;
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||||
size_t output_len;
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dma_addr_t data;
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size_t data_len;
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};
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struct brcm_message {
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enum brcm_message_type type;
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union {
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struct {
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struct brcm_message *msgs;
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unsigned int msgs_queued;
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unsigned int msgs_count;
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} batch;
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struct {
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||||
struct scatterlist *src;
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||||
struct scatterlist *dst;
|
||||
|
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|||
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