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drm/i915: Use genX_ prefix for gt irq enable/disable functions 

Traditionally we use genX_ for GT/render stuff and the codenames for
display stuff. But the gt and pm interrupt handling functions on
gen5/6+ stuck out as exceptions, so convert them.

Looking at the diff this nicely realigns our ducks since almost all
the callers are already platform-specific functions following the
genX_ pattern.

Spotted while reviewing some internal rps patches.

No function change in this patch.

Acked-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2014-07-16 09:49:40 +02:00
parent ca1381b55b
commit 480c803386
4 changed files with 26 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/gpu/drm/i915/i915_irq.c
View File

@ -182,12 +182,12 @@ static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
POSTING_READ(GTIMR); POSTING_READ(GTIMR);
} }
void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{ {
ilk_update_gt_irq(dev_priv, mask, mask); ilk_update_gt_irq(dev_priv, mask, mask);
} }
void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{ {
ilk_update_gt_irq(dev_priv, mask, 0); ilk_update_gt_irq(dev_priv, mask, 0);
} }
@ -220,12 +220,12 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
} }
} }
void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{ {
snb_update_pm_irq(dev_priv, mask, mask); snb_update_pm_irq(dev_priv, mask, mask);
} }
void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{ {
snb_update_pm_irq(dev_priv, mask, 0); snb_update_pm_irq(dev_priv, mask, 0);
} }
@ -278,12 +278,12 @@ static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
} }
} }
void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{ {
bdw_update_pm_irq(dev_priv, mask, mask); bdw_update_pm_irq(dev_priv, mask, mask);
} }
void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{ {
bdw_update_pm_irq(dev_priv, mask, 0); bdw_update_pm_irq(dev_priv, mask, 0);
} }
@ -1408,10 +1408,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
pm_iir = dev_priv->rps.pm_iir; pm_iir = dev_priv->rps.pm_iir;
dev_priv->rps.pm_iir = 0; dev_priv->rps.pm_iir = 0;
if (INTEL_INFO(dev_priv->dev)->gen >= 8) if (INTEL_INFO(dev_priv->dev)->gen >= 8)
bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
else { else {
/* Make sure not to corrupt PMIMR state used by ringbuffer */ /* Make sure not to corrupt PMIMR state used by ringbuffer */
snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
} }
spin_unlock_irq(&dev_priv->irq_lock); spin_unlock_irq(&dev_priv->irq_lock);
@ -1553,7 +1553,7 @@ static void ivybridge_parity_work(struct work_struct *work)
out: out:
WARN_ON(dev_priv->l3_parity.which_slice); WARN_ON(dev_priv->l3_parity.which_slice);
spin_lock_irqsave(&dev_priv->irq_lock, flags); spin_lock_irqsave(&dev_priv->irq_lock, flags);
ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
spin_unlock_irqrestore(&dev_priv->irq_lock, flags); spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
mutex_unlock(&dev_priv->dev->struct_mutex); mutex_unlock(&dev_priv->dev->struct_mutex);
@ -1567,7 +1567,7 @@ static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
return; return;
spin_lock(&dev_priv->irq_lock); spin_lock(&dev_priv->irq_lock);
ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
spin_unlock(&dev_priv->irq_lock); spin_unlock(&dev_priv->irq_lock);
iir &= GT_PARITY_ERROR(dev); iir &= GT_PARITY_ERROR(dev);
@ -1622,7 +1622,7 @@ static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
spin_lock(&dev_priv->irq_lock); spin_lock(&dev_priv->irq_lock);
dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
bdw_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
spin_unlock(&dev_priv->irq_lock); spin_unlock(&dev_priv->irq_lock);
queue_work(dev_priv->wq, &dev_priv->rps.work); queue_work(dev_priv->wq, &dev_priv->rps.work);
@ -1969,7 +1969,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
if (pm_iir & dev_priv->pm_rps_events) { if (pm_iir & dev_priv->pm_rps_events) {
spin_lock(&dev_priv->irq_lock); spin_lock(&dev_priv->irq_lock);
dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
spin_unlock(&dev_priv->irq_lock); spin_unlock(&dev_priv->irq_lock);
queue_work(dev_priv->wq, &dev_priv->rps.work); queue_work(dev_priv->wq, &dev_priv->rps.work);

12
drivers/gpu/drm/i915/intel_drv.h
View File

@ -683,12 +683,12 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
enum transcoder pch_transcoder, enum transcoder pch_transcoder,
bool enable); bool enable);
void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void bdw_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void intel_runtime_pm_disable_interrupts(struct drm_device *dev); void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
void intel_runtime_pm_restore_interrupts(struct drm_device *dev); void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
int intel_get_crtc_scanline(struct intel_crtc *crtc); int intel_get_crtc_scanline(struct intel_crtc *crtc);

4
drivers/gpu/drm/i915/intel_pm.c
View File

@ -3474,7 +3474,7 @@ static void gen8_enable_rps_interrupts(struct drm_device *dev)
spin_lock_irq(&dev_priv->irq_lock); spin_lock_irq(&dev_priv->irq_lock);
WARN_ON(dev_priv->rps.pm_iir); WARN_ON(dev_priv->rps.pm_iir);
bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events); I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
spin_unlock_irq(&dev_priv->irq_lock); spin_unlock_irq(&dev_priv->irq_lock);
} }
@ -3485,7 +3485,7 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev)
spin_lock_irq(&dev_priv->irq_lock); spin_lock_irq(&dev_priv->irq_lock);
WARN_ON(dev_priv->rps.pm_iir); WARN_ON(dev_priv->rps.pm_iir);
snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
spin_unlock_irq(&dev_priv->irq_lock); spin_unlock_irq(&dev_priv->irq_lock);
} }

12
drivers/gpu/drm/i915/intel_ringbuffer.c
View File

@ -1004,7 +1004,7 @@ gen5_ring_get_irq(struct intel_engine_cs *ring)
spin_lock_irqsave(&dev_priv->irq_lock, flags); spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (ring->irq_refcount++ == 0) if (ring->irq_refcount++ == 0)
ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
spin_unlock_irqrestore(&dev_priv->irq_lock, flags); spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
return true; return true;
@ -1019,7 +1019,7 @@ gen5_ring_put_irq(struct intel_engine_cs *ring)
spin_lock_irqsave(&dev_priv->irq_lock, flags); spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (--ring->irq_refcount == 0) if (--ring->irq_refcount == 0)
ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
spin_unlock_irqrestore(&dev_priv->irq_lock, flags); spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
} }
@ -1212,7 +1212,7 @@ gen6_ring_get_irq(struct intel_engine_cs *ring)
GT_PARITY_ERROR(dev))); GT_PARITY_ERROR(dev)));
else else
I915_WRITE_IMR(ring, ~ring->irq_enable_mask); I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
} }
spin_unlock_irqrestore(&dev_priv->irq_lock, flags); spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
@ -1232,7 +1232,7 @@ gen6_ring_put_irq(struct intel_engine_cs *ring)
I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
else else
I915_WRITE_IMR(ring, ~0); I915_WRITE_IMR(ring, ~0);
ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
} }
spin_unlock_irqrestore(&dev_priv->irq_lock, flags); spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
} }
@ -1250,7 +1250,7 @@ hsw_vebox_get_irq(struct intel_engine_cs *ring)
spin_lock_irqsave(&dev_priv->irq_lock, flags); spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (ring->irq_refcount++ == 0) { if (ring->irq_refcount++ == 0) {
I915_WRITE_IMR(ring, ~ring->irq_enable_mask); I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
} }
spin_unlock_irqrestore(&dev_priv->irq_lock, flags); spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
@ -1270,7 +1270,7 @@ hsw_vebox_put_irq(struct intel_engine_cs *ring)
spin_lock_irqsave(&dev_priv->irq_lock, flags); spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (--ring->irq_refcount == 0) { if (--ring->irq_refcount == 0) {
I915_WRITE_IMR(ring, ~0); I915_WRITE_IMR(ring, ~0);
snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
} }
spin_unlock_irqrestore(&dev_priv->irq_lock, flags); spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
} }