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Merge branch 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux into drm-next 

A few fixes for amdgpu and ttm for 4.8
- fix a ttm regression caused by the new pipelining code
- fixes for mullins on amdgpu
- updated golden settings for amdgpu

* 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux:
  drm/ttm: Wait for a BO to become idle before unbinding it from GTT
  drm/amdgpu: update golden setting of polaris10
  drm/amdgpu: update golden setting of stoney
  drm/amdgpu: update golden setting of polaris11
  drm/amdgpu: update golden setting of carrizo
  drm/amdgpu: update golden setting of iceland
  drm/amd/amdgpu: change pptable output format from ASCII to binary
  drm/amdgpu/ci: add mullins to default case for smc ucode
  drm/amdgpu/gmc7: add missing mullins case
This commit is contained in:
Dave Airlie 2016-08-08 16:45:33 +10:00
parent e8285cec4e 34b58355ad
commit 4872850a19
11 changed files with 39 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
View File

@ -305,7 +305,7 @@ static ssize_t amdgpu_get_pp_table(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev); struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private; struct amdgpu_device *adev = ddev->dev_private;
char *table = NULL; char *table = NULL;
int size, i; int size;
if (adev->pp_enabled) if (adev->pp_enabled)
size = amdgpu_dpm_get_pp_table(adev, &table); size = amdgpu_dpm_get_pp_table(adev, &table);
@ -315,10 +315,7 @@ static ssize_t amdgpu_get_pp_table(struct device *dev,
if (size >= PAGE_SIZE) if (size >= PAGE_SIZE)
size = PAGE_SIZE - 1; size = PAGE_SIZE - 1;
for (i = 0; i < size; i++) { memcpy(buf, table, size);
sprintf(buf + i, "%02x", table[i]);
}
sprintf(buf + i, "\n");
return size; return size;
} }

4
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
View File

@ -335,7 +335,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
if (unlikely(r)) { if (unlikely(r)) {
goto out_cleanup; goto out_cleanup;
} }
r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); r = ttm_bo_move_ttm(bo, true, interruptible, no_wait_gpu, new_mem);
out_cleanup: out_cleanup:
ttm_bo_mem_put(bo, &tmp_mem); ttm_bo_mem_put(bo, &tmp_mem);
return r; return r;
@ -368,7 +368,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
if (unlikely(r)) { if (unlikely(r)) {
return r; return r;
} }
r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); r = ttm_bo_move_ttm(bo, true, interruptible, no_wait_gpu, &tmp_mem);
if (unlikely(r)) { if (unlikely(r)) {
goto out_cleanup; goto out_cleanup;
} }

1
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
View File

@ -5779,6 +5779,7 @@ static int ci_dpm_init_microcode(struct amdgpu_device *adev)
break; break;
case CHIP_KAVERI: case CHIP_KAVERI:
case CHIP_KABINI: case CHIP_KABINI:
case CHIP_MULLINS:
default: BUG(); default: BUG();
} }

12
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
View File

@ -270,7 +270,8 @@ static const u32 tonga_mgcg_cgcg_init[] =
static const u32 golden_settings_polaris11_a11[] = static const u32 golden_settings_polaris11_a11[] =
{ {
mmCB_HW_CONTROL, 0xfffdf3cf, 0x00006208, mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
mmDB_DEBUG2, 0xf00fffff, 0x00000400, mmDB_DEBUG2, 0xf00fffff, 0x00000400,
mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
@ -279,7 +280,7 @@ static const u32 golden_settings_polaris11_a11[] =
mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c, mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
mmSQ_CONFIG, 0x07f80000, 0x07180000, mmSQ_CONFIG, 0x07f80000, 0x01180000,
mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
mmTCC_CTRL, 0x00100000, 0xf31fff7f, mmTCC_CTRL, 0x00100000, 0xf31fff7f,
mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3, mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
@ -301,8 +302,8 @@ static const u32 polaris11_golden_common_all[] =
static const u32 golden_settings_polaris10_a11[] = static const u32 golden_settings_polaris10_a11[] =
{ {
mmATC_MISC_CG, 0x000c0fc0, 0x000c0200, mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208, mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
mmCB_HW_CONTROL_2, 0, 0x0f000000, mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
mmDB_DEBUG2, 0xf00fffff, 0x00000400, mmDB_DEBUG2, 0xf00fffff, 0x00000400,
mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
@ -409,6 +410,7 @@ static const u32 golden_settings_iceland_a11[] =
mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002, mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
mmTCC_CTRL, 0x00100000, 0xf31fff7f, mmTCC_CTRL, 0x00100000, 0xf31fff7f,
@ -505,8 +507,10 @@ static const u32 cz_golden_settings_a11[] =
mmGB_GPU_ID, 0x0000000f, 0x00000000, mmGB_GPU_ID, 0x0000000f, 0x00000000,
mmPA_SC_ENHANCE, 0xffffffff, 0x00000001, mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
mmTA_CNTL_AUX, 0x000f000f, 0x00010000, mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
mmTCC_CTRL, 0x00100000, 0xf31fff7f,
mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3, mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302

1
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
View File

@ -144,6 +144,7 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
break; break;
case CHIP_KAVERI: case CHIP_KAVERI:
case CHIP_KABINI: case CHIP_KABINI:
case CHIP_MULLINS:
return 0; return 0;
default: BUG(); default: BUG();
} }

8
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
View File

@ -103,6 +103,11 @@ static const u32 stoney_mgcg_cgcg_init[] =
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
}; };
static const u32 golden_settings_stoney_common[] =
{
mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
};
static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
{ {
@ -142,6 +147,9 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
amdgpu_program_register_sequence(adev, amdgpu_program_register_sequence(adev,
stoney_mgcg_cgcg_init, stoney_mgcg_cgcg_init,
(const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_stoney_common,
(const u32)ARRAY_SIZE(golden_settings_stoney_common));
break; break;
default: default:
break; break;

4
drivers/gpu/drm/nouveau/nouveau_bo.c
View File

@ -1151,7 +1151,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
if (ret) if (ret)
goto out; goto out;
ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); ret = ttm_bo_move_ttm(bo, true, intr, no_wait_gpu, new_mem);
out: out:
ttm_bo_mem_put(bo, &tmp_mem); ttm_bo_mem_put(bo, &tmp_mem);
return ret; return ret;
@ -1179,7 +1179,7 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
if (ret) if (ret)
return ret; return ret;
ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); ret = ttm_bo_move_ttm(bo, true, intr, no_wait_gpu, &tmp_mem);
if (ret) if (ret)
goto out; goto out;

4
drivers/gpu/drm/radeon/radeon_ttm.c
View File

@ -346,7 +346,7 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
if (unlikely(r)) { if (unlikely(r)) {
goto out_cleanup; goto out_cleanup;
} }
r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); r = ttm_bo_move_ttm(bo, true, interruptible, no_wait_gpu, new_mem);
out_cleanup: out_cleanup:
ttm_bo_mem_put(bo, &tmp_mem); ttm_bo_mem_put(bo, &tmp_mem);
return r; return r;
@ -379,7 +379,7 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
if (unlikely(r)) { if (unlikely(r)) {
return r; return r;
} }
r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); r = ttm_bo_move_ttm(bo, true, interruptible, no_wait_gpu, &tmp_mem);
if (unlikely(r)) { if (unlikely(r)) {
goto out_cleanup; goto out_cleanup;
} }

3
drivers/gpu/drm/ttm/ttm_bo.c
View File

@ -354,7 +354,8 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo,
if (!(old_man->flags & TTM_MEMTYPE_FLAG_FIXED) && if (!(old_man->flags & TTM_MEMTYPE_FLAG_FIXED) &&
!(new_man->flags & TTM_MEMTYPE_FLAG_FIXED)) !(new_man->flags & TTM_MEMTYPE_FLAG_FIXED))
ret = ttm_bo_move_ttm(bo, evict, no_wait_gpu, mem); ret = ttm_bo_move_ttm(bo, evict, interruptible, no_wait_gpu,
mem);
else if (bdev->driver->move) else if (bdev->driver->move)
ret = bdev->driver->move(bo, evict, interruptible, ret = bdev->driver->move(bo, evict, interruptible,
no_wait_gpu, mem); no_wait_gpu, mem);

10
drivers/gpu/drm/ttm/ttm_bo_util.c
View File

@ -45,7 +45,7 @@ void ttm_bo_free_old_node(struct ttm_buffer_object *bo)
} }
int ttm_bo_move_ttm(struct ttm_buffer_object *bo, int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
bool evict, bool evict, bool interruptible,
bool no_wait_gpu, struct ttm_mem_reg *new_mem) bool no_wait_gpu, struct ttm_mem_reg *new_mem)
{ {
struct ttm_tt *ttm = bo->ttm; struct ttm_tt *ttm = bo->ttm;
@ -53,6 +53,14 @@ int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
int ret; int ret;
if (old_mem->mem_type != TTM_PL_SYSTEM) { if (old_mem->mem_type != TTM_PL_SYSTEM) {
ret = ttm_bo_wait(bo, interruptible, no_wait_gpu);
if (unlikely(ret != 0)) {
if (ret != -ERESTARTSYS)
pr_err("Failed to expire sync object before unbinding TTM\n");
return ret;
}
ttm_tt_unbind(ttm); ttm_tt_unbind(ttm);
ttm_bo_free_old_node(bo); ttm_bo_free_old_node(bo);
ttm_flag_masked(&old_mem->placement, TTM_PL_FLAG_SYSTEM, ttm_flag_masked(&old_mem->placement, TTM_PL_FLAG_SYSTEM,

3
include/drm/ttm/ttm_bo_driver.h
View File

@ -962,6 +962,7 @@ void ttm_mem_io_free(struct ttm_bo_device *bdev,
* *
* @bo: A pointer to a struct ttm_buffer_object. * @bo: A pointer to a struct ttm_buffer_object.
* @evict: 1: This is an eviction. Don't try to pipeline. * @evict: 1: This is an eviction. Don't try to pipeline.
* @interruptible: Sleep interruptible if waiting.
* @no_wait_gpu: Return immediately if the GPU is busy. * @no_wait_gpu: Return immediately if the GPU is busy.
* @new_mem: struct ttm_mem_reg indicating where to move. * @new_mem: struct ttm_mem_reg indicating where to move.
* *
@ -976,7 +977,7 @@ void ttm_mem_io_free(struct ttm_bo_device *bdev,
*/ */
extern int ttm_bo_move_ttm(struct ttm_buffer_object *bo, extern int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
bool evict, bool no_wait_gpu, bool evict, bool interruptible, bool no_wait_gpu,
struct ttm_mem_reg *new_mem); struct ttm_mem_reg *new_mem);
/** /**