mirror of https://gitee.com/openkylin/linux.git
dsa: mv88e6xxx: Kill the REG_READ and REG_WRITE macros
These macros hide a ds variable and a return statement on error, which can lead to locking issues. Kill them off. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Andrew Lunn
David S. Miller
parent
756ca87441
commit
48ace4ef4c
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@ -52,7 +52,9 @@ static int mv88e6123_setup_global(struct dsa_switch *ds)
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* external PHYs to poll), don't discard packets with
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* excessive collisions, and mask all interrupt sources.
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*/
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REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, 0x0000);
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL, 0x0000);
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if (ret)
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return ret;
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/* Configure the upstream port, and configure the upstream
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* port as the port to which ingress and egress monitor frames
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@ -61,14 +63,15 @@ static int mv88e6123_setup_global(struct dsa_switch *ds)
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reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
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upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
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upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
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REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
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if (ret)
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return ret;
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/* Disable remote management for now, and set the switch's
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* DSA device number.
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*/
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REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, ds->index & 0x1f);
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return 0;
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return mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL_2,
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ds->index & 0x1f);
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}
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static int mv88e6123_setup(struct dsa_switch *ds)
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@ -49,11 +49,16 @@ static int mv88e6131_setup_global(struct dsa_switch *ds)
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* to arbitrate between packet queues, set the maximum frame
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* size to 1632, and mask all interrupt sources.
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*/
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REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
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GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_MAX_FRAME_1632);
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL,
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GLOBAL_CONTROL_PPU_ENABLE |
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GLOBAL_CONTROL_MAX_FRAME_1632);
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if (ret)
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return ret;
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/* Set the VLAN ethertype to 0x8100. */
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REG_WRITE(REG_GLOBAL, GLOBAL_CORE_TAG_TYPE, 0x8100);
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CORE_TAG_TYPE, 0x8100);
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if (ret)
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return ret;
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/* Disable ARP mirroring, and configure the upstream port as
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* the port to which ingress and egress monitor frames are to
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@ -62,31 +67,33 @@ static int mv88e6131_setup_global(struct dsa_switch *ds)
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reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
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upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
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GLOBAL_MONITOR_CONTROL_ARP_DISABLED;
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REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
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if (ret)
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return ret;
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/* Disable cascade port functionality unless this device
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* is used in a cascade configuration, and set the switch's
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* DSA device number.
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*/
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if (ds->dst->pd->nr_chips > 1)
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REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2,
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GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
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(ds->index & 0x1f));
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL_2,
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GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
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(ds->index & 0x1f));
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else
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REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2,
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GLOBAL_CONTROL_2_NO_CASCADE |
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(ds->index & 0x1f));
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL_2,
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GLOBAL_CONTROL_2_NO_CASCADE |
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(ds->index & 0x1f));
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if (ret)
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return ret;
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/* Force the priority of IGMP/MLD snoop frames and ARP frames
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* to the highest setting.
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*/
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REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
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GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP |
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7 << GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT |
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GLOBAL2_PRIO_OVERRIDE_FORCE_ARP |
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7 << GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT);
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return 0;
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return mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
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GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP |
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7 << GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT |
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GLOBAL2_PRIO_OVERRIDE_FORCE_ARP |
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7 << GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT);
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}
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static int mv88e6131_setup(struct dsa_switch *ds)
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@ -46,8 +46,11 @@ static int mv88e6171_setup_global(struct dsa_switch *ds)
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/* Discard packets with excessive collisions, mask all
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* interrupt sources, enable PPU.
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*/
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REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
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GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_DISCARD_EXCESS);
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL,
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GLOBAL_CONTROL_PPU_ENABLE |
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GLOBAL_CONTROL_DISCARD_EXCESS);
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if (ret)
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return ret;
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/* Configure the upstream port, and configure the upstream
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* port as the port to which ingress and egress monitor frames
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@ -57,14 +60,15 @@ static int mv88e6171_setup_global(struct dsa_switch *ds)
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upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
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upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT |
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upstream_port << GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT;
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REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
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if (ret)
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return ret;
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/* Disable remote management for now, and set the switch's
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* DSA device number.
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*/
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REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, ds->index & 0x1f);
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return 0;
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return mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL_2,
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ds->index & 0x1f);
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}
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static int mv88e6171_setup(struct dsa_switch *ds)
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@ -59,8 +59,11 @@ static int mv88e6352_setup_global(struct dsa_switch *ds)
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/* Discard packets with excessive collisions,
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* mask all interrupt sources, enable PPU (bit 14, undocumented).
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*/
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REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
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GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_DISCARD_EXCESS);
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL,
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GLOBAL_CONTROL_PPU_ENABLE |
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GLOBAL_CONTROL_DISCARD_EXCESS);
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if (ret)
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return ret;
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/* Configure the upstream port, and configure the upstream
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* port as the port to which ingress and egress monitor frames
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@ -69,14 +72,14 @@ static int mv88e6352_setup_global(struct dsa_switch *ds)
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reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
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upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
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upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
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REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
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if (ret)
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return ret;
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/* Disable remote management for now, and set the switch's
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* DSA device number.
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*/
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REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
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return 0;
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return mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1c, ds->index & 0x1f);
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}
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static int mv88e6352_setup(struct dsa_switch *ds)
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@ -180,28 +180,44 @@ int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
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int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
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{
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REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
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REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
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REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
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int err;
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return 0;
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err = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MAC_01,
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(addr[0] << 8) | addr[1]);
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if (err)
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return err;
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err = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MAC_23,
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(addr[2] << 8) | addr[3]);
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if (err)
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return err;
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return mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MAC_45,
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(addr[4] << 8) | addr[5]);
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}
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int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
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{
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int i;
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int ret;
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int i;
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for (i = 0; i < 6; i++) {
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int j;
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/* Write the MAC address byte. */
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REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
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GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
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GLOBAL2_SWITCH_MAC_BUSY |
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(i << 8) | addr[i]);
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if (ret)
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return ret;
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/* Wait for the write to complete. */
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for (j = 0; j < 16; j++) {
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ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
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ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2,
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GLOBAL2_SWITCH_MAC);
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if (ret < 0)
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return ret;
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if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
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break;
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}
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@ -233,13 +249,21 @@ static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
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int ret;
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unsigned long timeout;
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ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
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REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
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ret & ~GLOBAL_CONTROL_PPU_ENABLE);
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ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_CONTROL);
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if (ret < 0)
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return ret;
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL,
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ret & ~GLOBAL_CONTROL_PPU_ENABLE);
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if (ret)
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return ret;
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timeout = jiffies + 1 * HZ;
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while (time_before(jiffies, timeout)) {
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ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
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ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATUS);
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if (ret < 0)
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return ret;
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usleep_range(1000, 2000);
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if ((ret & GLOBAL_STATUS_PPU_MASK) !=
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GLOBAL_STATUS_PPU_POLLING)
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@ -251,15 +275,24 @@ static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
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static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
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{
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int ret;
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int ret, err;
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unsigned long timeout;
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ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
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REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
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ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_CONTROL);
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if (ret < 0)
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return ret;
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err = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL,
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ret | GLOBAL_CONTROL_PPU_ENABLE);
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if (err)
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return err;
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timeout = jiffies + 1 * HZ;
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while (time_before(jiffies, timeout)) {
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ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
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ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATUS);
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if (ret < 0)
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return ret;
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usleep_range(1000, 2000);
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if ((ret & GLOBAL_STATUS_PPU_MASK) ==
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GLOBAL_STATUS_PPU_POLLING)
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@ -2667,7 +2700,9 @@ int mv88e6xxx_setup_common(struct dsa_switch *ds)
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ps->ds = ds;
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mutex_init(&ps->smi_mutex);
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ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
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ps->id = mv88e6xxx_reg_read(ds, REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
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if (ps->id < 0)
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return ps->id;
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INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
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@ -2677,42 +2712,67 @@ int mv88e6xxx_setup_common(struct dsa_switch *ds)
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int mv88e6xxx_setup_global(struct dsa_switch *ds)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int ret;
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int err;
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int i;
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mutex_lock(&ps->smi_mutex);
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/* Set the default address aging time to 5 minutes, and
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* enable address learn messages to be sent to all message
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* ports.
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*/
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REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
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0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
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err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL,
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0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
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if (err)
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goto unlock;
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/* Configure the IP ToS mapping registers. */
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REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
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REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
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REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
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REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
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REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
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REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
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REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
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REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
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err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
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if (err)
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goto unlock;
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err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
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if (err)
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goto unlock;
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err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
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if (err)
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goto unlock;
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err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
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if (err)
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goto unlock;
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err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
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if (err)
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goto unlock;
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err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
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if (err)
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goto unlock;
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err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
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if (err)
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goto unlock;
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err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
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if (err)
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goto unlock;
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/* Configure the IEEE 802.1p priority mapping register. */
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REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
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err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
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if (err)
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goto unlock;
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/* Send all frames with destination addresses matching
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* 01:80:c2:00:00:0x to the CPU port.
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*/
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REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
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err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
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if (err)
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goto unlock;
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/* Ignore removed tag data on doubly tagged packets, disable
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* flow control messages, force flow control priority to the
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* highest, and send all special multicast frames to the CPU
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* port at the highest priority.
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*/
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REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
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0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
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GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
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err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
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0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
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GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
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if (err)
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goto unlock;
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/* Program the DSA routing table. */
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for (i = 0; i < 32; i++) {
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@ -2722,23 +2782,35 @@ int mv88e6xxx_setup_global(struct dsa_switch *ds)
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i != ds->index && i < ds->dst->pd->nr_chips)
|
||||
nexthop = ds->pd->rtable[i] & 0x1f;
|
||||
|
||||
REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
|
||||
GLOBAL2_DEVICE_MAPPING_UPDATE |
|
||||
(i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
|
||||
nexthop);
|
||||
err = _mv88e6xxx_reg_write(
|
||||
ds, REG_GLOBAL2,
|
||||
GLOBAL2_DEVICE_MAPPING,
|
||||
GLOBAL2_DEVICE_MAPPING_UPDATE |
|
||||
(i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop);
|
||||
if (err)
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
/* Clear all trunk masks. */
|
||||
for (i = 0; i < 8; i++)
|
||||
REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
|
||||
0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
|
||||
((1 << ps->num_ports) - 1));
|
||||
for (i = 0; i < 8; i++) {
|
||||
err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
|
||||
0x8000 |
|
||||
(i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
|
||||
((1 << ps->num_ports) - 1));
|
||||
if (err)
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
/* Clear all trunk mappings. */
|
||||
for (i = 0; i < 16; i++)
|
||||
REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
|
||||
GLOBAL2_TRUNK_MAPPING_UPDATE |
|
||||
(i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
|
||||
for (i = 0; i < 16; i++) {
|
||||
err = _mv88e6xxx_reg_write(
|
||||
ds, REG_GLOBAL2,
|
||||
GLOBAL2_TRUNK_MAPPING,
|
||||
GLOBAL2_TRUNK_MAPPING_UPDATE |
|
||||
(i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
|
||||
if (err)
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
|
||||
mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
|
||||
|
|
@ -2746,17 +2818,27 @@ int mv88e6xxx_setup_global(struct dsa_switch *ds)
|
|||
/* Send all frames with destination addresses matching
|
||||
* 01:80:c2:00:00:2x to the CPU port.
|
||||
*/
|
||||
REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
|
||||
err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2,
|
||||
GLOBAL2_MGMT_EN_2X, 0xffff);
|
||||
if (err)
|
||||
goto unlock;
|
||||
|
||||
/* Initialise cross-chip port VLAN table to reset
|
||||
* defaults.
|
||||
*/
|
||||
REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
|
||||
err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2,
|
||||
GLOBAL2_PVT_ADDR, 0x9000);
|
||||
if (err)
|
||||
goto unlock;
|
||||
|
||||
/* Clear the priority override table. */
|
||||
for (i = 0; i < 16; i++)
|
||||
REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
|
||||
0x8000 | (i << 8));
|
||||
for (i = 0; i < 16; i++) {
|
||||
err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2,
|
||||
GLOBAL2_PRIO_OVERRIDE,
|
||||
0x8000 | (i << 8));
|
||||
if (err)
|
||||
goto unlock;
|
||||
}
|
||||
}
|
||||
|
||||
if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
|
||||
|
|
@ -2767,31 +2849,37 @@ int mv88e6xxx_setup_global(struct dsa_switch *ds)
|
|||
* ingress rate limit registers to their initial
|
||||
* state.
|
||||
*/
|
||||
for (i = 0; i < ps->num_ports; i++)
|
||||
REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
|
||||
0x9000 | (i << 8));
|
||||
for (i = 0; i < ps->num_ports; i++) {
|
||||
err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2,
|
||||
GLOBAL2_INGRESS_OP,
|
||||
0x9000 | (i << 8));
|
||||
if (err)
|
||||
goto unlock;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the statistics counters for all ports */
|
||||
REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
|
||||
err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
|
||||
GLOBAL_STATS_OP_FLUSH_ALL);
|
||||
if (err)
|
||||
goto unlock;
|
||||
|
||||
/* Wait for the flush to complete. */
|
||||
mutex_lock(&ps->smi_mutex);
|
||||
ret = _mv88e6xxx_stats_wait(ds);
|
||||
if (ret < 0)
|
||||
err = _mv88e6xxx_stats_wait(ds);
|
||||
if (err < 0)
|
||||
goto unlock;
|
||||
|
||||
/* Clear all ATU entries */
|
||||
ret = _mv88e6xxx_atu_flush(ds, 0, true);
|
||||
if (ret < 0)
|
||||
err = _mv88e6xxx_atu_flush(ds, 0, true);
|
||||
if (err < 0)
|
||||
goto unlock;
|
||||
|
||||
/* Clear all the VTU and STU entries */
|
||||
ret = _mv88e6xxx_vtu_stu_flush(ds);
|
||||
err = _mv88e6xxx_vtu_stu_flush(ds);
|
||||
unlock:
|
||||
mutex_unlock(&ps->smi_mutex);
|
||||
|
||||
return ret;
|
||||
return err;
|
||||
}
|
||||
|
||||
int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
|
||||
|
|
@ -2803,10 +2891,18 @@ int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
|
|||
int ret;
|
||||
int i;
|
||||
|
||||
mutex_lock(&ps->smi_mutex);
|
||||
|
||||
/* Set all ports to the disabled state. */
|
||||
for (i = 0; i < ps->num_ports; i++) {
|
||||
ret = REG_READ(REG_PORT(i), PORT_CONTROL);
|
||||
REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
|
||||
ret = _mv88e6xxx_reg_read(ds, REG_PORT(i), PORT_CONTROL);
|
||||
if (ret < 0)
|
||||
goto unlock;
|
||||
|
||||
ret = _mv88e6xxx_reg_write(ds, REG_PORT(i), PORT_CONTROL,
|
||||
ret & 0xfffc);
|
||||
if (ret)
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
/* Wait for transmit queues to drain. */
|
||||
|
|
@ -2825,22 +2921,31 @@ int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
|
|||
* through global registers 0x18 and 0x19.
|
||||
*/
|
||||
if (ppu_active)
|
||||
REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
|
||||
ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x04, 0xc000);
|
||||
else
|
||||
REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
|
||||
ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x04, 0xc400);
|
||||
if (ret)
|
||||
goto unlock;
|
||||
|
||||
/* Wait up to one second for reset to complete. */
|
||||
timeout = jiffies + 1 * HZ;
|
||||
while (time_before(jiffies, timeout)) {
|
||||
ret = REG_READ(REG_GLOBAL, 0x00);
|
||||
ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x00);
|
||||
if (ret < 0)
|
||||
goto unlock;
|
||||
|
||||
if ((ret & is_reset) == is_reset)
|
||||
break;
|
||||
usleep_range(1000, 2000);
|
||||
}
|
||||
if (time_after(jiffies, timeout))
|
||||
return -ETIMEDOUT;
|
||||
ret = -ETIMEDOUT;
|
||||
else
|
||||
ret = 0;
|
||||
unlock:
|
||||
mutex_unlock(&ps->smi_mutex);
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
|
||||
|
|
|
|||
|
|
@ -542,25 +542,4 @@ extern struct dsa_switch_driver mv88e6123_switch_driver;
|
|||
extern struct dsa_switch_driver mv88e6352_switch_driver;
|
||||
extern struct dsa_switch_driver mv88e6171_switch_driver;
|
||||
|
||||
#define REG_READ(addr, reg) \
|
||||
({ \
|
||||
int __ret; \
|
||||
\
|
||||
__ret = mv88e6xxx_reg_read(ds, addr, reg); \
|
||||
if (__ret < 0) \
|
||||
return __ret; \
|
||||
__ret; \
|
||||
})
|
||||
|
||||
#define REG_WRITE(addr, reg, val) \
|
||||
({ \
|
||||
int __ret; \
|
||||
\
|
||||
__ret = mv88e6xxx_reg_write(ds, addr, reg, val); \
|
||||
if (__ret < 0) \
|
||||
return __ret; \
|
||||
})
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue