mirror of https://gitee.com/openkylin/linux.git
drm/radeon/kms: add support for CP setup on SI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
8b074dd640
commit
48c0c902e2
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@ -71,7 +71,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
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r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
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evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
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radeon_trace_points.o ni.o cayman_blit_shaders.o atombios_encoders.o \
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radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o
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radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o si_blit_shaders.o
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radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
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radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
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@ -31,6 +31,7 @@
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#include "radeon_drm.h"
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#include "sid.h"
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#include "atom.h"
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#include "si_blit_shaders.h"
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#define SI_PFP_UCODE_SIZE 2144
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#define SI_PM4_UCODE_SIZE 2144
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@ -1861,6 +1862,272 @@ static void si_gpu_init(struct radeon_device *rdev)
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udelay(50);
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}
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/*
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* CP.
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*/
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static void si_cp_enable(struct radeon_device *rdev, bool enable)
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{
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if (enable)
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WREG32(CP_ME_CNTL, 0);
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else {
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
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WREG32(SCRATCH_UMSK, 0);
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}
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udelay(50);
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}
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static int si_cp_load_microcode(struct radeon_device *rdev)
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{
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const __be32 *fw_data;
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int i;
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if (!rdev->me_fw || !rdev->pfp_fw)
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return -EINVAL;
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si_cp_enable(rdev, false);
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/* PFP */
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fw_data = (const __be32 *)rdev->pfp_fw->data;
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WREG32(CP_PFP_UCODE_ADDR, 0);
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for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
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WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
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WREG32(CP_PFP_UCODE_ADDR, 0);
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/* CE */
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fw_data = (const __be32 *)rdev->ce_fw->data;
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WREG32(CP_CE_UCODE_ADDR, 0);
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for (i = 0; i < SI_CE_UCODE_SIZE; i++)
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WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
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WREG32(CP_CE_UCODE_ADDR, 0);
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/* ME */
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fw_data = (const __be32 *)rdev->me_fw->data;
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WREG32(CP_ME_RAM_WADDR, 0);
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for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
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WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
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WREG32(CP_ME_RAM_WADDR, 0);
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WREG32(CP_PFP_UCODE_ADDR, 0);
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WREG32(CP_CE_UCODE_ADDR, 0);
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WREG32(CP_ME_RAM_WADDR, 0);
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WREG32(CP_ME_RAM_RADDR, 0);
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return 0;
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}
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static int si_cp_start(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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int r, i;
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r = radeon_ring_lock(rdev, ring, 7 + 4);
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if (r) {
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DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
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return r;
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}
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/* init the CP */
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radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
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radeon_ring_write(ring, 0x1);
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radeon_ring_write(ring, 0x0);
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radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
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radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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/* init the CE partitions */
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radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
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radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
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radeon_ring_write(ring, 0xc000);
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radeon_ring_write(ring, 0xe000);
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radeon_ring_unlock_commit(rdev, ring);
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si_cp_enable(rdev, true);
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r = radeon_ring_lock(rdev, ring, si_default_size + 10);
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if (r) {
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DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
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return r;
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}
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/* setup clear context state */
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radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
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for (i = 0; i < si_default_size; i++)
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radeon_ring_write(ring, si_default_state[i]);
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radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
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/* set clear context state */
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radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
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radeon_ring_write(ring, 0x00000316);
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radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
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radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
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radeon_ring_unlock_commit(rdev, ring);
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for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
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ring = &rdev->ring[i];
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r = radeon_ring_lock(rdev, ring, 2);
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/* clear the compute context state */
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radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_unlock_commit(rdev, ring);
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}
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return 0;
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}
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static void si_cp_fini(struct radeon_device *rdev)
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{
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si_cp_enable(rdev, false);
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radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
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radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
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radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
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}
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static int si_cp_resume(struct radeon_device *rdev)
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{
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struct radeon_ring *ring;
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u32 tmp;
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u32 rb_bufsz;
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int r;
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/* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
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WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
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SOFT_RESET_PA |
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SOFT_RESET_VGT |
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SOFT_RESET_SPI |
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SOFT_RESET_SX));
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RREG32(GRBM_SOFT_RESET);
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mdelay(15);
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WREG32(GRBM_SOFT_RESET, 0);
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RREG32(GRBM_SOFT_RESET);
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WREG32(CP_SEM_WAIT_TIMER, 0x0);
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WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
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/* Set the write pointer delay */
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WREG32(CP_RB_WPTR_DELAY, 0);
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WREG32(CP_DEBUG, 0);
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WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
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/* ring 0 - compute and gfx */
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/* Set ring buffer size */
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ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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rb_bufsz = drm_order(ring->ring_size / 8);
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tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
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#ifdef __BIG_ENDIAN
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tmp |= BUF_SWAP_32BIT;
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#endif
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WREG32(CP_RB0_CNTL, tmp);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
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ring->wptr = 0;
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WREG32(CP_RB0_WPTR, ring->wptr);
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/* set the wb address wether it's enabled or not */
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WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
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WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
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if (rdev->wb.enabled)
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WREG32(SCRATCH_UMSK, 0xff);
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else {
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tmp |= RB_NO_UPDATE;
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WREG32(SCRATCH_UMSK, 0);
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}
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mdelay(1);
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WREG32(CP_RB0_CNTL, tmp);
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WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
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ring->rptr = RREG32(CP_RB0_RPTR);
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/* ring1 - compute only */
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/* Set ring buffer size */
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ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
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rb_bufsz = drm_order(ring->ring_size / 8);
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tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
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#ifdef __BIG_ENDIAN
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tmp |= BUF_SWAP_32BIT;
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#endif
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WREG32(CP_RB1_CNTL, tmp);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
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ring->wptr = 0;
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WREG32(CP_RB1_WPTR, ring->wptr);
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/* set the wb address wether it's enabled or not */
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WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
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WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
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mdelay(1);
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WREG32(CP_RB1_CNTL, tmp);
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WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
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ring->rptr = RREG32(CP_RB1_RPTR);
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/* ring2 - compute only */
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/* Set ring buffer size */
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ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
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rb_bufsz = drm_order(ring->ring_size / 8);
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tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
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#ifdef __BIG_ENDIAN
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tmp |= BUF_SWAP_32BIT;
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#endif
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WREG32(CP_RB2_CNTL, tmp);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
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ring->wptr = 0;
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WREG32(CP_RB2_WPTR, ring->wptr);
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/* set the wb address wether it's enabled or not */
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WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
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WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
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mdelay(1);
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WREG32(CP_RB2_CNTL, tmp);
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WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
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ring->rptr = RREG32(CP_RB2_RPTR);
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/* start the rings */
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si_cp_start(rdev);
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
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rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
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rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
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r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
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if (r) {
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
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rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
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rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
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return r;
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}
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r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
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if (r) {
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rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
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}
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r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
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if (r) {
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rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
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}
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return 0;
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}
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bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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u32 srbm_status;
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@ -0,0 +1,252 @@
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/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Alex Deucher <alexander.deucher@amd.com>
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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const u32 si_default_state[] =
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{
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0xc0066900,
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0x00000000,
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0x00000060, /* DB_RENDER_CONTROL */
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0x00000000, /* DB_COUNT_CONTROL */
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0x00000000, /* DB_DEPTH_VIEW */
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0x0000002a, /* DB_RENDER_OVERRIDE */
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0x00000000, /* DB_RENDER_OVERRIDE2 */
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0x00000000, /* DB_HTILE_DATA_BASE */
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0xc0046900,
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0x00000008,
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0x00000000, /* DB_DEPTH_BOUNDS_MIN */
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0x00000000, /* DB_DEPTH_BOUNDS_MAX */
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0x00000000, /* DB_STENCIL_CLEAR */
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0x00000000, /* DB_DEPTH_CLEAR */
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0xc0036900,
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0x0000000f,
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0x00000000, /* DB_DEPTH_INFO */
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0x00000000, /* DB_Z_INFO */
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0x00000000, /* DB_STENCIL_INFO */
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0xc0016900,
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0x00000080,
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0x00000000, /* PA_SC_WINDOW_OFFSET */
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0xc00d6900,
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0x00000083,
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0x0000ffff, /* PA_SC_CLIPRECT_RULE */
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0x00000000, /* PA_SC_CLIPRECT_0_TL */
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0x20002000, /* PA_SC_CLIPRECT_0_BR */
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0x00000000,
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0x20002000,
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0x00000000,
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0x20002000,
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0x00000000,
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0x20002000,
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0xaaaaaaaa, /* PA_SC_EDGERULE */
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0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
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0x0000000f, /* CB_TARGET_MASK */
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0x0000000f, /* CB_SHADER_MASK */
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0xc0226900,
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0x00000094,
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0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
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0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x00000000, /* PA_SC_VPORT_ZMIN_0 */
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0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
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0xc0026900,
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0x000000d9,
|
||||
0x00000000, /* CP_RINGID */
|
||||
0x00000000, /* CP_VMID */
|
||||
|
||||
0xc0046900,
|
||||
0x00000100,
|
||||
0xffffffff, /* VGT_MAX_VTX_INDX */
|
||||
0x00000000, /* VGT_MIN_VTX_INDX */
|
||||
0x00000000, /* VGT_INDX_OFFSET */
|
||||
0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
|
||||
|
||||
0xc0046900,
|
||||
0x00000105,
|
||||
0x00000000, /* CB_BLEND_RED */
|
||||
0x00000000, /* CB_BLEND_GREEN */
|
||||
0x00000000, /* CB_BLEND_BLUE */
|
||||
0x00000000, /* CB_BLEND_ALPHA */
|
||||
|
||||
0xc0016900,
|
||||
0x000001e0,
|
||||
0x00000000, /* CB_BLEND0_CONTROL */
|
||||
|
||||
0xc00e6900,
|
||||
0x00000200,
|
||||
0x00000000, /* DB_DEPTH_CONTROL */
|
||||
0x00000000, /* DB_EQAA */
|
||||
0x00cc0010, /* CB_COLOR_CONTROL */
|
||||
0x00000210, /* DB_SHADER_CONTROL */
|
||||
0x00010000, /* PA_CL_CLIP_CNTL */
|
||||
0x00000004, /* PA_SU_SC_MODE_CNTL */
|
||||
0x00000100, /* PA_CL_VTE_CNTL */
|
||||
0x00000000, /* PA_CL_VS_OUT_CNTL */
|
||||
0x00000000, /* PA_CL_NANINF_CNTL */
|
||||
0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
|
||||
0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
|
||||
0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
|
||||
0xc0116900,
|
||||
0x00000280,
|
||||
0x00000000, /* PA_SU_POINT_SIZE */
|
||||
0x00000000, /* PA_SU_POINT_MINMAX */
|
||||
0x00000008, /* PA_SU_LINE_CNTL */
|
||||
0x00000000, /* PA_SC_LINE_STIPPLE */
|
||||
0x00000000, /* VGT_OUTPUT_PATH_CNTL */
|
||||
0x00000000, /* VGT_HOS_CNTL */
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000, /* VGT_GS_MODE */
|
||||
|
||||
0xc0026900,
|
||||
0x00000292,
|
||||
0x00000000, /* PA_SC_MODE_CNTL_0 */
|
||||
0x00000000, /* PA_SC_MODE_CNTL_1 */
|
||||
|
||||
0xc0016900,
|
||||
0x000002a1,
|
||||
0x00000000, /* VGT_PRIMITIVEID_EN */
|
||||
|
||||
0xc0016900,
|
||||
0x000002a5,
|
||||
0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
|
||||
|
||||
0xc0026900,
|
||||
0x000002a8,
|
||||
0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
|
||||
0x00000000,
|
||||
|
||||
0xc0026900,
|
||||
0x000002ad,
|
||||
0x00000000, /* VGT_REUSE_OFF */
|
||||
0x00000000,
|
||||
|
||||
0xc0016900,
|
||||
0x000002d5,
|
||||
0x00000000, /* VGT_SHADER_STAGES_EN */
|
||||
|
||||
0xc0016900,
|
||||
0x000002dc,
|
||||
0x0000aa00, /* DB_ALPHA_TO_MASK */
|
||||
|
||||
0xc0066900,
|
||||
0x000002de,
|
||||
0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
0xc0026900,
|
||||
0x000002e5,
|
||||
0x00000000, /* VGT_STRMOUT_CONFIG */
|
||||
0x00000000,
|
||||
|
||||
0xc01b6900,
|
||||
0x000002f5,
|
||||
0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
|
||||
0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
|
||||
0x00000000, /* PA_SC_LINE_CNTL */
|
||||
0x00000000, /* PA_SC_AA_CONFIG */
|
||||
0x00000005, /* PA_SU_VTX_CNTL */
|
||||
0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
|
||||
0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
|
||||
0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
|
||||
0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
|
||||
0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
|
||||
0xffffffff,
|
||||
|
||||
0xc0026900,
|
||||
0x00000316,
|
||||
0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
|
||||
0x00000010, /* */
|
||||
};
|
||||
|
||||
const u32 si_default_size = ARRAY_SIZE(si_default_state);
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SI_BLIT_SHADERS_H
|
||||
#define SI_BLIT_SHADERS_H
|
||||
|
||||
extern const u32 si_default_state[];
|
||||
|
||||
extern const u32 si_default_size;
|
||||
|
||||
#endif
|
||||
|
|
@ -273,12 +273,31 @@
|
|||
|
||||
#define GRBM_GFX_INDEX 0x802C
|
||||
|
||||
#define SCRATCH_REG0 0x8500
|
||||
#define SCRATCH_REG1 0x8504
|
||||
#define SCRATCH_REG2 0x8508
|
||||
#define SCRATCH_REG3 0x850C
|
||||
#define SCRATCH_REG4 0x8510
|
||||
#define SCRATCH_REG5 0x8514
|
||||
#define SCRATCH_REG6 0x8518
|
||||
#define SCRATCH_REG7 0x851C
|
||||
|
||||
#define SCRATCH_UMSK 0x8540
|
||||
#define SCRATCH_ADDR 0x8544
|
||||
|
||||
#define CP_SEM_WAIT_TIMER 0x85BC
|
||||
|
||||
#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
|
||||
|
||||
#define CP_ME_CNTL 0x86D8
|
||||
#define CP_CE_HALT (1 << 24)
|
||||
#define CP_PFP_HALT (1 << 26)
|
||||
#define CP_ME_HALT (1 << 28)
|
||||
|
||||
#define CP_RB2_RPTR 0x86f8
|
||||
#define CP_RB1_RPTR 0x86fc
|
||||
#define CP_RB0_RPTR 0x8700
|
||||
#define CP_RB_WPTR_DELAY 0x8704
|
||||
|
||||
#define CP_QUEUE_THRESHOLDS 0x8760
|
||||
#define ROQ_IB1_START(x) ((x) << 0)
|
||||
|
|
@ -458,6 +477,40 @@
|
|||
#define TCP_CHAN_STEER_LO 0xac0c
|
||||
#define TCP_CHAN_STEER_HI 0xac10
|
||||
|
||||
#define CP_RB0_BASE 0xC100
|
||||
#define CP_RB0_CNTL 0xC104
|
||||
#define RB_BUFSZ(x) ((x) << 0)
|
||||
#define RB_BLKSZ(x) ((x) << 8)
|
||||
#define BUF_SWAP_32BIT (2 << 16)
|
||||
#define RB_NO_UPDATE (1 << 27)
|
||||
#define RB_RPTR_WR_ENA (1 << 31)
|
||||
|
||||
#define CP_RB0_RPTR_ADDR 0xC10C
|
||||
#define CP_RB0_RPTR_ADDR_HI 0xC110
|
||||
#define CP_RB0_WPTR 0xC114
|
||||
|
||||
#define CP_PFP_UCODE_ADDR 0xC150
|
||||
#define CP_PFP_UCODE_DATA 0xC154
|
||||
#define CP_ME_RAM_RADDR 0xC158
|
||||
#define CP_ME_RAM_WADDR 0xC15C
|
||||
#define CP_ME_RAM_DATA 0xC160
|
||||
|
||||
#define CP_CE_UCODE_ADDR 0xC168
|
||||
#define CP_CE_UCODE_DATA 0xC16C
|
||||
|
||||
#define CP_RB1_BASE 0xC180
|
||||
#define CP_RB1_CNTL 0xC184
|
||||
#define CP_RB1_RPTR_ADDR 0xC188
|
||||
#define CP_RB1_RPTR_ADDR_HI 0xC18C
|
||||
#define CP_RB1_WPTR 0xC190
|
||||
#define CP_RB2_BASE 0xC194
|
||||
#define CP_RB2_CNTL 0xC198
|
||||
#define CP_RB2_RPTR_ADDR 0xC19C
|
||||
#define CP_RB2_RPTR_ADDR_HI 0xC1A0
|
||||
#define CP_RB2_WPTR 0xC1A4
|
||||
|
||||
#define CP_DEBUG 0xC1FC
|
||||
|
||||
/*
|
||||
* PM4
|
||||
*/
|
||||
|
|
@ -483,6 +536,8 @@
|
|||
(((op) & 0xFF) << 8) | \
|
||||
((n) & 0x3FFF) << 16)
|
||||
|
||||
#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
|
||||
|
||||
/* Packet 3 types */
|
||||
#define PACKET3_NOP 0x10
|
||||
#define PACKET3_SET_BASE 0x11
|
||||
|
|
|
|||
Loading…
Reference in New Issue