mirror of https://gitee.com/openkylin/linux.git
cleanup unused codes for samsung
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRYuOXAAoJEA0Cl+kVi2xq75EP/0DkQ2vJP6pESS2V7vq57/0K lnbeXxdZGwQAYuNNdtYXTT30yCr8AJ5AtD7tdyXMu33BCj0EJIBswX/jBVRNwZ0M RXdUoLaldyccoc7COav/pptKViEteNmYFkMN6++Bx24clsugZ+upJv95HGeCnO6P zW5KpsJdNNvJCoqfQxsoQEFAHOR9qS9Wve+hZaoSTJtDyQw2H87XxDo2M0bxeu0W Zpo9fnwOitMPAkiUV8Q0oHDdoDrL0wmH1OsXaKihc7KCCgT0+3aDkpMKxMV7AfaB w8TxPIZym2ko4cY/6SeLQEZ/GCCgcCxBRyMvZ0SzWnU5zSSoB+yZMzVbYxwslSdE 21tfGJVyo/E2a0CzcLHSCKHXtShswYNWREfRgozp6q5/Ys6j7fqXi34Hoo2iAtIK KNBTinZDBAco3TjOCimnluJ5CEHP6Hvd8uqXfqDM525TZWeGTDBKykj0l7ECYwdb zB/blf8BHwJV4UgvTPJG1RXsyVJWDXyKzQ9+uJJG7zDiFsjeaQqPhcedxJOdkLlM fSjm+PcS/buhkIyob7tjBO/VYs4uQuwVEI+PbM8ITRMprMUJ78KNsVHaEjjqJlGq xIusneCGUs6dwQr/fY8FIboV/1QVNi2ioL+F83NILdSBucY8iXtN+OzHg1nTbuEZ WJto47UQVuWe/QfFlr/C =Imcz -----END PGP SIGNATURE----- Merge tag 'cleanup-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup From Kukjin Kim <kgene.kim@samsung.com>: cleanup unused codes for samsung * tag 'cleanup-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: remove "config EXYNOS_DEV_DRM" ARM: EXYNOS: change the name of USB ohci header ARM: SAMSUNG: Remove unnecessary code for dma ARM: S3C24XX: Remove unused GPIO drive strength register definitions ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2412 ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2410 ARM: S3C24XX: Removed unneeded dependency on ARCH_S3C24XX for boards ARM: SAMSUNG: Fix typo "CONFIG_SAMSUNG_DEV_RTC" ARM: S5P64X0: Fix typo "CONFIG_S5P64X0_SETUP_SDHCI" ARM: S3C64XX: remove obsolete Makefile line ARM: S3C24XX: remove unneeded "config SMDK2440_CPU2442" ARM: SAMSUNG: Remove useless Samsung GPIO related CONFIG ARM: SAMSUNG: remove "config S3C_BOOT_WATCHDOG" ARM: EXYNOS: change HAVE_SAMSUNG_KEYPAD to KEYBOARD_SAMSUNG ARM: EXYNOS: remove duplicated include from common.c ARM: EXYNOS: drop "select HAVE_SCHED_CLOCK" ARM: S3C24XX: drop "select MACH_NEO1973" ARM: S3C24XX: drop "select MACH_N35" Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
4909e13cd9
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@ -1175,7 +1175,6 @@ config PLAT_VERSATILE
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config ARM_TIMER_SP804
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bool
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select CLKSRC_MMIO
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select HAVE_SCHED_CLOCK
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source arch/arm/mm/Kconfig
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@ -95,11 +95,6 @@ config EXYNOS4_DEV_AHCI
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help
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Compile in platform device definitions for AHCI
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config EXYNOS_DEV_DRM
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bool
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help
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Compile in platform device definitions for core DRM device
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config EXYNOS4_SETUP_FIMD0
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bool
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help
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@ -199,7 +194,6 @@ config MACH_SMDKV310
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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select EXYNOS_DEV_DMA
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select EXYNOS_DEV_DRM
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select EXYNOS_DEV_SYSMMU
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select S3C24XX_PWM
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select S3C_DEV_HSMMC
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@ -253,9 +247,7 @@ config MACH_UNIVERSAL_C210
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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select EXYNOS_DEV_DMA
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select EXYNOS_DEV_DRM
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select EXYNOS_DEV_SYSMMU
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select HAVE_SCHED_CLOCK
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select S3C_DEV_HSMMC
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select S3C_DEV_HSMMC2
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select S3C_DEV_HSMMC3
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@ -294,7 +286,6 @@ config MACH_NURI
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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select EXYNOS_DEV_DMA
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select EXYNOS_DEV_DRM
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select S3C_DEV_HSMMC
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select S3C_DEV_HSMMC2
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select S3C_DEV_HSMMC3
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@ -330,7 +321,6 @@ config MACH_ORIGEN
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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select EXYNOS_DEV_DMA
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select EXYNOS_DEV_DRM
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select EXYNOS_DEV_SYSMMU
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select S3C24XX_PWM
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select S3C_DEV_HSMMC
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@ -366,7 +356,6 @@ config MACH_SMDK4212
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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select EXYNOS_DEV_DMA
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select EXYNOS_DEV_DRM
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select EXYNOS_DEV_SYSMMU
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select S3C24XX_PWM
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select S3C_DEV_HSMMC2
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@ -407,7 +396,7 @@ config MACH_EXYNOS4_DT
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depends on ARCH_EXYNOS4
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select ARM_AMBA
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select CPU_EXYNOS4210
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select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
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select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
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select PINCTRL
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select PINCTRL_EXYNOS
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select USE_OF
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@ -23,7 +23,6 @@
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#include <linux/of_irq.h>
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#include <linux/export.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/chained_irq.h>
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@ -12,7 +12,7 @@
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/usb-exynos.h>
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#include <linux/platform_data/usb-ohci-exynos.h>
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#include <mach/irqs.h>
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#include <mach/map.h>
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@ -26,7 +26,7 @@
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#include <linux/platform_data/i2c-s3c2410.h>
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#include <linux/platform_data/s3c-hsotg.h>
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#include <linux/platform_data/usb-ehci-s5p.h>
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#include <linux/platform_data/usb-exynos.h>
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#include <linux/platform_data/usb-ohci-exynos.h>
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#include <asm/mach/arch.h>
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#include <asm/mach-types.h>
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@ -23,7 +23,7 @@
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#include <linux/platform_data/i2c-s3c2410.h>
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#include <linux/platform_data/s3c-hsotg.h>
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#include <linux/platform_data/usb-ehci-s5p.h>
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#include <linux/platform_data/usb-exynos.h>
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#include <linux/platform_data/usb-ohci-exynos.h>
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#include <asm/mach/arch.h>
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#include <asm/mach-types.h>
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@ -36,7 +36,6 @@ config CPU_S3C2410
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config CPU_S3C2412
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bool "SAMSUNG S3C2412"
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depends on ARCH_S3C24XX
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select CPU_ARM926T
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select CPU_LLSERIAL_S3C2440
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select S3C2412_DMA if S3C24XX_DMA
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@ -46,7 +45,6 @@ config CPU_S3C2412
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config CPU_S3C2416
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bool "SAMSUNG S3C2416/S3C2450"
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depends on ARCH_S3C24XX
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select CPU_ARM926T
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select CPU_LLSERIAL_S3C2440
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select S3C2416_PM if PM
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@ -81,7 +79,6 @@ config CPU_S3C244X
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config CPU_S3C2443
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bool "SAMSUNG S3C2443"
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depends on ARCH_S3C24XX
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select CPU_ARM920T
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select CPU_LLSERIAL_S3C2440
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select S3C2443_COMMON
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@ -133,7 +130,6 @@ config S3C24XX_SETUP_TS
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config S3C24XX_DMA
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bool "S3C2410 DMA support"
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depends on ARCH_S3C24XX
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select S3C_DMA
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help
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S3C2410 DMA support. This is needed for drivers like sound which
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@ -142,7 +138,7 @@ config S3C24XX_DMA
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config S3C2410_DMA_DEBUG
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bool "S3C2410 DMA support debug"
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depends on ARCH_S3C24XX && S3C2410_DMA
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depends on S3C2410_DMA
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help
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Enable debugging output for the DMA code. This option sends info
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to the kernel log, at priority KERN_DEBUG.
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@ -233,7 +229,7 @@ if CPU_S3C2410
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config S3C2410_CPUFREQ
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bool
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depends on CPU_FREQ_S3C24XX && CPU_S3C2410
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depends on CPU_FREQ_S3C24XX
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select S3C2410_CPUFREQ_UTILS
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help
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CPU Frequency scaling support for S3C2410
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@ -320,7 +316,6 @@ config PM_H1940
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config MACH_N30
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bool "Acer N30 family"
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select MACH_N35
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select S3C_DEV_NAND
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select S3C_DEV_USB_HOST
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help
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@ -380,14 +375,13 @@ if CPU_S3C2412
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config CPU_S3C2412_ONLY
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bool
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depends on ARCH_S3C24XX && !CPU_S3C2410 && \
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!CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
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!CPU_S3C2443 && CPU_S3C2412
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depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \
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!CPU_S3C2442 && !CPU_S3C2443
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default y
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config S3C2412_CPUFREQ
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bool
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depends on CPU_FREQ_S3C24XX && CPU_S3C2412
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depends on CPU_FREQ_S3C24XX
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default y
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select S3C2412_IOTIMING
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help
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@ -642,7 +636,6 @@ comment "S3C2442 Boards"
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config MACH_NEO1973_GTA02
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bool "Openmoko GTA02 / Freerunner phone"
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select I2C
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select MACH_NEO1973
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select MFD_PCF50633
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select PCF50633_GPIO
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select POWER_SUPPLY
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@ -663,10 +656,7 @@ config MACH_RX1950
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help
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Say Y here if you're using HP iPAQ rx1950
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config SMDK2440_CPU2442
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bool "SMDM2440 with S3C2442 CPU module"
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endif # CPU_S3C2440
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endif # CPU_S3C2442
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if CPU_S3C2443 || CPU_S3C2416
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@ -24,7 +24,6 @@
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*/
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enum dma_ch {
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DMACH_DT_PROP = -1, /* not yet supported, do not use */
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DMACH_XD0 = 0,
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DMACH_XD1,
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DMACH_SDI,
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@ -1,5 +1,4 @@
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/* arch/arm/mach-s3c2410/include/mach/regs-dsc.h
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*
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/*
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* Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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@ -12,209 +11,15 @@
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#ifndef __ASM_ARCH_REGS_DSC_H
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#define __ASM_ARCH_REGS_DSC_H "2440-dsc"
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#define __ASM_ARCH_REGS_DSC_H __FILE__
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#if defined(CONFIG_CPU_S3C2412)
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/* S3C2412 */
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#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc)
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#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
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#endif
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#if defined(CONFIG_CPU_S3C2416)
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#define S3C2416_DSC0 S3C2410_GPIOREG(0xc0)
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#define S3C2416_DSC1 S3C2410_GPIOREG(0xc4)
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#define S3C2416_DSC2 S3C2410_GPIOREG(0xc8)
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#define S3C2416_DSC3 S3C2410_GPIOREG(0x110)
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#define S3C2416_SELECT_DSC0 (0 << 30)
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#define S3C2416_SELECT_DSC1 (1 << 30)
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#define S3C2416_SELECT_DSC2 (2 << 30)
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#define S3C2416_SELECT_DSC3 (3 << 30)
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#define S3C2416_DSC_GETSHIFT(x) (x & 30)
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#define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28)
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#define S3C2416_DSC0_CF_5mA (0 << 28)
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#define S3C2416_DSC0_CF_10mA (1 << 28)
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#define S3C2416_DSC0_CF_15mA (2 << 28)
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#define S3C2416_DSC0_CF_21mA (3 << 28)
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#define S3C2416_DSC0_CF_MASK (3 << 28)
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#define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26)
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#define S3C2416_DSC0_nRBE_5mA (0 << 26)
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#define S3C2416_DSC0_nRBE_10mA (1 << 26)
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#define S3C2416_DSC0_nRBE_15mA (2 << 26)
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#define S3C2416_DSC0_nRBE_21mA (3 << 26)
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#define S3C2416_DSC0_nRBE_MASK (3 << 26)
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#define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24)
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#define S3C2416_DSC0_nROE_5mA (0 << 24)
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#define S3C2416_DSC0_nROE_10mA (1 << 24)
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#define S3C2416_DSC0_nROE_15mA (2 << 24)
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#define S3C2416_DSC0_nROE_21mA (3 << 24)
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#define S3C2416_DSC0_nROE_MASK (3 << 24)
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#endif
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#if defined(CONFIG_CPU_S3C244X)
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/* S3C2440 */
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#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
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#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
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#define S3C2440_SELECT_DSC0 (0)
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#define S3C2440_SELECT_DSC1 (1<<31)
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#define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
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#define S3C2440_DSC0_DISABLE (1<<31)
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#define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8)
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#define S3C2440_DSC0_ADDR_12mA (0<<8)
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#define S3C2440_DSC0_ADDR_10mA (1<<8)
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#define S3C2440_DSC0_ADDR_8mA (2<<8)
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#define S3C2440_DSC0_ADDR_6mA (3<<8)
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#define S3C2440_DSC0_ADDR_MASK (3<<8)
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/* D24..D31 */
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#define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6)
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#define S3C2440_DSC0_DATA3_12mA (0<<6)
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#define S3C2440_DSC0_DATA3_10mA (1<<6)
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#define S3C2440_DSC0_DATA3_8mA (2<<6)
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#define S3C2440_DSC0_DATA3_6mA (3<<6)
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#define S3C2440_DSC0_DATA3_MASK (3<<6)
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/* D16..D23 */
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#define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4)
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#define S3C2440_DSC0_DATA2_12mA (0<<4)
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#define S3C2440_DSC0_DATA2_10mA (1<<4)
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#define S3C2440_DSC0_DATA2_8mA (2<<4)
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#define S3C2440_DSC0_DATA2_6mA (3<<4)
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#define S3C2440_DSC0_DATA2_MASK (3<<4)
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/* D8..D15 */
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#define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2)
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#define S3C2440_DSC0_DATA1_12mA (0<<2)
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#define S3C2440_DSC0_DATA1_10mA (1<<2)
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#define S3C2440_DSC0_DATA1_8mA (2<<2)
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#define S3C2440_DSC0_DATA1_6mA (3<<2)
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#define S3C2440_DSC0_DATA1_MASK (3<<2)
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/* D0..D7 */
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#define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0)
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#define S3C2440_DSC0_DATA0_12mA (0<<0)
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#define S3C2440_DSC0_DATA0_10mA (1<<0)
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#define S3C2440_DSC0_DATA0_8mA (2<<0)
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#define S3C2440_DSC0_DATA0_6mA (3<<0)
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#define S3C2440_DSC0_DATA0_MASK (3<<0)
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#define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28)
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#define S3C2440_DSC1_SCK1_12mA (0<<28)
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#define S3C2440_DSC1_SCK1_10mA (1<<28)
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#define S3C2440_DSC1_SCK1_8mA (2<<28)
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#define S3C2440_DSC1_SCK1_6mA (3<<28)
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#define S3C2440_DSC1_SCK1_MASK (3<<28)
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|
||||
#define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26)
|
||||
#define S3C2440_DSC1_SCK0_12mA (0<<26)
|
||||
#define S3C2440_DSC1_SCK0_10mA (1<<26)
|
||||
#define S3C2440_DSC1_SCK0_8mA (2<<26)
|
||||
#define S3C2440_DSC1_SCK0_6mA (3<<26)
|
||||
#define S3C2440_DSC1_SCK0_MASK (3<<26)
|
||||
|
||||
#define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24)
|
||||
#define S3C2440_DSC1_SCKE_10mA (0<<24)
|
||||
#define S3C2440_DSC1_SCKE_8mA (1<<24)
|
||||
#define S3C2440_DSC1_SCKE_6mA (2<<24)
|
||||
#define S3C2440_DSC1_SCKE_4mA (3<<24)
|
||||
#define S3C2440_DSC1_SCKE_MASK (3<<24)
|
||||
|
||||
/* SDRAM nRAS/nCAS */
|
||||
#define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22)
|
||||
#define S3C2440_DSC1_SDR_10mA (0<<22)
|
||||
#define S3C2440_DSC1_SDR_8mA (1<<22)
|
||||
#define S3C2440_DSC1_SDR_6mA (2<<22)
|
||||
#define S3C2440_DSC1_SDR_4mA (3<<22)
|
||||
#define S3C2440_DSC1_SDR_MASK (3<<22)
|
||||
|
||||
/* NAND Flash Controller */
|
||||
#define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20)
|
||||
#define S3C2440_DSC1_NFC_10mA (0<<20)
|
||||
#define S3C2440_DSC1_NFC_8mA (1<<20)
|
||||
#define S3C2440_DSC1_NFC_6mA (2<<20)
|
||||
#define S3C2440_DSC1_NFC_4mA (3<<20)
|
||||
#define S3C2440_DSC1_NFC_MASK (3<<20)
|
||||
|
||||
/* nBE[0..3] */
|
||||
#define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18)
|
||||
#define S3C2440_DSC1_nBE_10mA (0<<18)
|
||||
#define S3C2440_DSC1_nBE_8mA (1<<18)
|
||||
#define S3C2440_DSC1_nBE_6mA (2<<18)
|
||||
#define S3C2440_DSC1_nBE_4mA (3<<18)
|
||||
#define S3C2440_DSC1_nBE_MASK (3<<18)
|
||||
|
||||
#define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16)
|
||||
#define S3C2440_DSC1_WOE_10mA (0<<16)
|
||||
#define S3C2440_DSC1_WOE_8mA (1<<16)
|
||||
#define S3C2440_DSC1_WOE_6mA (2<<16)
|
||||
#define S3C2440_DSC1_WOE_4mA (3<<16)
|
||||
#define S3C2440_DSC1_WOE_MASK (3<<16)
|
||||
|
||||
#define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14)
|
||||
#define S3C2440_DSC1_CS7_10mA (0<<14)
|
||||
#define S3C2440_DSC1_CS7_8mA (1<<14)
|
||||
#define S3C2440_DSC1_CS7_6mA (2<<14)
|
||||
#define S3C2440_DSC1_CS7_4mA (3<<14)
|
||||
#define S3C2440_DSC1_CS7_MASK (3<<14)
|
||||
|
||||
#define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12)
|
||||
#define S3C2440_DSC1_CS6_10mA (0<<12)
|
||||
#define S3C2440_DSC1_CS6_8mA (1<<12)
|
||||
#define S3C2440_DSC1_CS6_6mA (2<<12)
|
||||
#define S3C2440_DSC1_CS6_4mA (3<<12)
|
||||
#define S3C2440_DSC1_CS6_MASK (3<<12)
|
||||
|
||||
#define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10)
|
||||
#define S3C2440_DSC1_CS5_10mA (0<<10)
|
||||
#define S3C2440_DSC1_CS5_8mA (1<<10)
|
||||
#define S3C2440_DSC1_CS5_6mA (2<<10)
|
||||
#define S3C2440_DSC1_CS5_4mA (3<<10)
|
||||
#define S3C2440_DSC1_CS5_MASK (3<<10)
|
||||
|
||||
#define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8)
|
||||
#define S3C2440_DSC1_CS4_10mA (0<<8)
|
||||
#define S3C2440_DSC1_CS4_8mA (1<<8)
|
||||
#define S3C2440_DSC1_CS4_6mA (2<<8)
|
||||
#define S3C2440_DSC1_CS4_4mA (3<<8)
|
||||
#define S3C2440_DSC1_CS4_MASK (3<<8)
|
||||
|
||||
#define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6)
|
||||
#define S3C2440_DSC1_CS3_10mA (0<<6)
|
||||
#define S3C2440_DSC1_CS3_8mA (1<<6)
|
||||
#define S3C2440_DSC1_CS3_6mA (2<<6)
|
||||
#define S3C2440_DSC1_CS3_4mA (3<<6)
|
||||
#define S3C2440_DSC1_CS3_MASK (3<<6)
|
||||
|
||||
#define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4)
|
||||
#define S3C2440_DSC1_CS2_10mA (0<<4)
|
||||
#define S3C2440_DSC1_CS2_8mA (1<<4)
|
||||
#define S3C2440_DSC1_CS2_6mA (2<<4)
|
||||
#define S3C2440_DSC1_CS2_4mA (3<<4)
|
||||
#define S3C2440_DSC1_CS2_MASK (3<<4)
|
||||
|
||||
#define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2)
|
||||
#define S3C2440_DSC1_CS1_10mA (0<<2)
|
||||
#define S3C2440_DSC1_CS1_8mA (1<<2)
|
||||
#define S3C2440_DSC1_CS1_6mA (2<<2)
|
||||
#define S3C2440_DSC1_CS1_4mA (3<<2)
|
||||
#define S3C2440_DSC1_CS1_MASK (3<<2)
|
||||
|
||||
#define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0)
|
||||
#define S3C2440_DSC1_CS0_10mA (0<<0)
|
||||
#define S3C2440_DSC1_CS0_8mA (1<<0)
|
||||
#define S3C2440_DSC1_CS0_6mA (2<<0)
|
||||
#define S3C2440_DSC1_CS0_4mA (3<<0)
|
||||
#define S3C2440_DSC1_CS0_MASK (3<<0)
|
||||
|
||||
#endif /* CONFIG_CPU_S3C2440 */
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_DSC_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -32,7 +32,6 @@ obj-$(CONFIG_S3C64XX_DMA) += dma.o
|
|||
|
||||
obj-y += dev-uart.o
|
||||
obj-y += dev-audio.o
|
||||
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
|
||||
|
||||
# Device setup
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@
|
|||
*/
|
||||
enum dma_ch {
|
||||
/* DMA0/SDMA0 */
|
||||
DMACH_DT_PROP = -1, /* not yet supported, do not use */
|
||||
DMACH_UART0 = 0,
|
||||
DMACH_UART0_SRC2,
|
||||
DMACH_UART1,
|
||||
|
|
|
|||
|
|
@ -37,14 +37,6 @@ if PLAT_SAMSUNG
|
|||
|
||||
comment "Boot options"
|
||||
|
||||
config S3C_BOOT_WATCHDOG
|
||||
bool "S3C Initialisation watchdog"
|
||||
depends on S3C2410_WATCHDOG
|
||||
help
|
||||
Say y to enable the watchdog during the kernel decompression
|
||||
stage. If the kernel fails to uncompress, then the watchdog
|
||||
will trigger a reset and the system should restart.
|
||||
|
||||
config S3C_BOOT_ERROR_RESET
|
||||
bool "S3C Reboot on decompression error"
|
||||
help
|
||||
|
|
@ -125,12 +117,6 @@ config SAMSUNG_GPIOLIB_4BIT
|
|||
configuration. GPIOlib shall be compiled only for S3C64XX and S5P
|
||||
series of processors.
|
||||
|
||||
config S3C_GPIO_CFG_S3C64XX
|
||||
bool
|
||||
help
|
||||
Internal configuration to enable S3C64XX style GPIO configuration
|
||||
functions.
|
||||
|
||||
config S5P_GPIO_DRVSTR
|
||||
bool
|
||||
help
|
||||
|
|
|
|||
|
|
@ -23,23 +23,15 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
|
|||
struct device *dev, char *ch_name)
|
||||
{
|
||||
dma_cap_mask_t mask;
|
||||
void *filter_param;
|
||||
|
||||
dma_cap_zero(mask);
|
||||
dma_cap_set(param->cap, mask);
|
||||
|
||||
/*
|
||||
* If a dma channel property of a device node from device tree is
|
||||
* specified, use that as the fliter parameter.
|
||||
*/
|
||||
filter_param = (dma_ch == DMACH_DT_PROP) ?
|
||||
(void *)param->dt_dmach_prop : (void *)dma_ch;
|
||||
|
||||
if (dev->of_node)
|
||||
return (unsigned)dma_request_slave_channel(dev, ch_name);
|
||||
else
|
||||
return (unsigned)dma_request_channel(mask, pl330_filter,
|
||||
filter_param);
|
||||
(void *)dma_ch);
|
||||
}
|
||||
|
||||
static int samsung_dmadev_release(unsigned ch, void *param)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
|
||||
struct samsung_dma_req {
|
||||
enum dma_transaction_type cap;
|
||||
struct property *dt_dmach_prop;
|
||||
struct s3c2410_dma_client *client;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@
|
|||
* use these just as IDs.
|
||||
*/
|
||||
enum dma_ch {
|
||||
DMACH_DT_PROP = -1,
|
||||
DMACH_UART0_RX = 0,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
/* re-define device name depending on support. */
|
||||
static inline void s3c_rtc_setname(char *name)
|
||||
{
|
||||
#if defined(CONFIG_SAMSUNG_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX)
|
||||
#if defined(CONFIG_S3C_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX)
|
||||
s3c_device_rtc.name = name;
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -206,7 +206,7 @@ static inline void s3c6400_default_sdhci2(void) { }
|
|||
|
||||
/* S5P64X0 SDHCI setup */
|
||||
|
||||
#ifdef CONFIG_S5P64X0_SETUP_SDHCI
|
||||
#ifdef CONFIG_S5P64X0_SETUP_SDHCI_GPIO
|
||||
static inline void s5p64x0_default_sdhci0(void)
|
||||
{
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC
|
||||
|
|
@ -241,7 +241,7 @@ static inline void s5p64x0_default_sdhci1(void) { }
|
|||
static inline void s5p6440_default_sdhci2(void) { }
|
||||
static inline void s5p6450_default_sdhci2(void) { }
|
||||
|
||||
#endif /* CONFIG_S5P64X0_SETUP_SDHCI */
|
||||
#endif /* CONFIG_S5P64X0_SETUP_SDHCI_GPIO */
|
||||
|
||||
/* S5PC100 SDHCI setup */
|
||||
|
||||
|
|
|
|||
|
|
@ -14,9 +14,10 @@
|
|||
#include <linux/clk.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/platform_data/usb-exynos.h>
|
||||
#include <linux/platform_data/usb-ohci-exynos.h>
|
||||
#include <linux/usb/phy.h>
|
||||
#include <linux/usb/samsung_usb_phy.h>
|
||||
|
||||
#include <plat/usb-phy.h>
|
||||
|
||||
struct exynos_ohci_hcd {
|
||||
|
|
|
|||
Loading…
Reference in New Issue