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drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context 

Since ggtt_offset_bias is now stored in ggtt.pin_bias, it is duplicated
inside i915_gem_context, and can instead be accessed directly from ggtt.

v3:
Added a helper function to retrieve the ggtt.pin_bias from the vma.

v4:
Moved the helper function to the previous patch in the series.
Dropped the bias from intel_ring_pin. This introduces a slight functional
change since we are always pinning the ring a bit higher if GuC is present
even though we don't really need to.

v8:
Fixed patch not applying on the most recent upstream.

Signed-off-by: Jakub Bartmiński <jakub.bartminski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180727141148.30874-4-jakub.bartminski@intel.com
This commit is contained in:
Jakub Bartmiński 2018-07-27 16:11:46 +02:00 committed by Chris Wilson
parent dd18cedfa3
commit 496bcce3c9
5 changed files with 9 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/i915_gem_context.c
View File

@ -329,8 +329,6 @@ __create_hw_context(struct drm_i915_private *dev_priv,
ctx->desc_template =
default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
ctx->ggtt_offset_bias = dev_priv->ggtt.pin_bias;
return ctx;
err_pid:

3
drivers/gpu/drm/i915/i915_gem_context.h
View File

@ -147,9 +147,6 @@ struct i915_gem_context {
struct i915_sched_attr sched;
/** ggtt_offset_bias: placement restriction for context objects */
u32 ggtt_offset_bias;
/** engine: per-engine logical HW state */
struct intel_context {
struct i915_gem_context *gem_context;

5
drivers/gpu/drm/i915/intel_lrc.c
View File

@ -1303,8 +1303,7 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
}
flags = PIN_GLOBAL | PIN_HIGH;
if (ctx->ggtt_offset_bias)
flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
return i915_vma_pin(vma, 0, 0, flags);
}
@ -1332,7 +1331,7 @@ __execlists_context_pin(struct intel_engine_cs *engine,
goto unpin_vma;
}
ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
ret = intel_ring_pin(ce->ring, ctx->i915);
if (ret)
goto unpin_map;

16
drivers/gpu/drm/i915/intel_ringbuffer.c
View File

@ -1003,11 +1003,7 @@ i915_emit_bb_start(struct i915_request *rq,
return 0;
}
int intel_ring_pin(struct intel_ring *ring,
struct drm_i915_private *i915,
unsigned int offset_bias)
int intel_ring_pin(struct intel_ring *ring, struct drm_i915_private *i915)
{
enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
struct i915_vma *vma = ring->vma;
@ -1017,10 +1013,11 @@ int intel_ring_pin(struct intel_ring *ring,
GEM_BUG_ON(ring->vaddr);
flags = PIN_GLOBAL;
if (offset_bias)
flags |= PIN_OFFSET_BIAS | offset_bias;
/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
if (vma->obj->stolen)
flags |= PIN_MAPPABLE;
else
@ -1408,8 +1405,7 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
goto err;
}
/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE);
err = intel_ring_pin(ring, engine->i915);
if (err)
goto err_ring;

4
drivers/gpu/drm/i915/intel_ringbuffer.h
View File

@ -797,9 +797,7 @@ struct intel_ring *
intel_engine_create_ring(struct intel_engine_cs *engine,
struct i915_timeline *timeline,
int size);
int intel_ring_pin(struct intel_ring *ring,
struct drm_i915_private *i915,
unsigned int offset_bias);
int intel_ring_pin(struct intel_ring *ring, struct drm_i915_private *i915);
void intel_ring_reset(struct intel_ring *ring, u32 tail);
unsigned int intel_ring_update_space(struct intel_ring *ring);
void intel_ring_unpin(struct intel_ring *ring);