mirror of https://gitee.com/openkylin/linux.git
OMAP PM cleanups for v3.10
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRZJmAAAoJEFk3GJrT+8ZlZ5IQAIXNen7upyNtYSeDUtrc1FXR GiDv03QB92IKSh+PB4t8PhTsngwipv7gVY790q1GneULU4rzY65o2EOlGhc5qGop PgCcuWrIcjf8YCD9KB07iwYZ2ovCZXpsc/IeV3OYvJYSptpXMPZD1+jP7XuaBIHN 3+oPmDtTRH0vqZXskN+MhNkDB59yZWQ1HjfWfZsS872T5TEUpg8A6kaBC6JmELYh ZEY1cydt6650RIM2jARznN1X4AfO+2WpA3e8fvvNJ9g9tAckb3Sr5SM9QVtjiRtM LCRJejYkP3EzrywBrhWRHPRd+Sz6HQk46YPbY8H5y1cMPWORP21E+xTwOEAzYibj cRZfK++OmrVaPKem2HKsZI6Xok1Mhw7/dP913b6RtZNxSRcnh8xFKhvG0y5xVmkV S/p39bvbIo6kUQrsuxVPbm2yjZ4d/UzY4dsov0fNKpa2FEfHPgE+WDKAHABIVZdj QZDA+uQvybwaiisW3DO80C9I05diAXfXEphepQHc02Mzkmci967aOKHRvNGE5/f4 XCWeNyLSC6HXHdoxZ98DZb+TdTWQz6Fl+28LdBCgDVBr6R1SLQn8ShKYjqTpnwNo fq07DGEC98igrfQ7RTFDKKFoOGyy8+oShJMQZbub/kUgbcjqhvqIis88ZAmtTZHB mkRGeA34zdfcFkfTLFxv =wNGR -----END PGP SIGNATURE----- Merge tag 'omap-pm-v3.10/cleanup/pm' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-for-v3.11/pm OMAP PM cleanups for v3.10
This commit is contained in:
Tony Lindgren
commit
49a34fd538
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@ -237,8 +237,8 @@ extern void omap_do_wfi(void);
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#ifdef CONFIG_SMP
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/* Needed for secondary core boot */
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extern void omap_secondary_startup(void);
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extern void omap_secondary_startup_4460(void);
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extern void omap4_secondary_startup(void);
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extern void omap4460_secondary_startup(void);
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extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
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extern void omap_auxcoreboot_addr(u32 cpu_addr);
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extern u32 omap_read_auxcoreboot0(void);
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@ -49,7 +49,7 @@ END(omap5_secondary_startup)
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* The primary core will update this flag using a hardware
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* register AuxCoreBoot0.
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*/
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ENTRY(omap_secondary_startup)
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ENTRY(omap4_secondary_startup)
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hold: ldr r12,=0x103
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dsb
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smc #0 @ read from AuxCoreBoot0
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@ -64,9 +64,9 @@ hold: ldr r12,=0x103
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(omap_secondary_startup)
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ENDPROC(omap4_secondary_startup)
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ENTRY(omap_secondary_startup_4460)
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ENTRY(omap4460_secondary_startup)
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hold_2: ldr r12,=0x103
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dsb
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smc #0 @ read from AuxCoreBoot0
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@ -101,4 +101,4 @@ hold_2: ldr r12,=0x103
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(omap_secondary_startup_4460)
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ENDPROC(omap4460_secondary_startup)
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@ -71,10 +71,43 @@ struct omap4_cpu_pm_info {
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void (*secondary_startup)(void);
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};
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/**
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* struct cpu_pm_ops - CPU pm operations
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* @finish_suspend: CPU suspend finisher function pointer
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* @resume: CPU resume function pointer
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* @scu_prepare: CPU Snoop Control program function pointer
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*
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* Structure holds functions pointer for CPU low power operations like
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* suspend, resume and scu programming.
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*/
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struct cpu_pm_ops {
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int (*finish_suspend)(unsigned long cpu_state);
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void (*resume)(void);
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void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
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};
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static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
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static struct powerdomain *mpuss_pd;
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static void __iomem *sar_base;
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static int default_finish_suspend(unsigned long cpu_state)
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{
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omap_do_wfi();
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return 0;
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}
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static void dummy_cpu_resume(void)
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{}
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static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
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{}
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struct cpu_pm_ops omap_pm_ops = {
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.finish_suspend = default_finish_suspend,
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.resume = dummy_cpu_resume,
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.scu_prepare = dummy_scu_prepare,
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};
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/*
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* Program the wakeup routine address for the CPU0 and CPU1
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* used for OFF or DORMANT wakeup.
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@ -158,11 +191,12 @@ static void save_l2x0_context(void)
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{
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u32 val;
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void __iomem *l2x0_base = omap4_get_l2cache_base();
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val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
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__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
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val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
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__raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
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if (l2x0_base) {
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val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
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__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
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val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
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__raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
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}
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}
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#else
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static void save_l2x0_context(void)
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@ -225,14 +259,17 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
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cpu_clear_prev_logic_pwrst(cpu);
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pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
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set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
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scu_pwrst_prepare(cpu, power_state);
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set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
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omap_pm_ops.scu_prepare(cpu, power_state);
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l2x0_pwrst_prepare(cpu, save_state);
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/*
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* Call low level function with targeted low power state.
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*/
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cpu_suspend(save_state, omap4_finish_suspend);
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if (save_state)
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cpu_suspend(save_state, omap_pm_ops.finish_suspend);
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else
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omap_pm_ops.finish_suspend(save_state);
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/*
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* Restore the CPUx power state to ON otherwise CPUx
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@ -268,14 +305,14 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
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pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
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pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
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set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
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scu_pwrst_prepare(cpu, power_state);
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omap_pm_ops.scu_prepare(cpu, power_state);
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/*
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* CPU never retuns back if targeted power state is OFF mode.
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* CPU ONLINE follows normal CPU ONLINE ptah via
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* omap_secondary_startup().
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* omap4_secondary_startup().
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*/
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omap4_finish_suspend(cpu_state);
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omap_pm_ops.finish_suspend(cpu_state);
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pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
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return 0;
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@ -319,9 +356,9 @@ int __init omap4_mpuss_init(void)
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pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
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pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
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if (cpu_is_omap446x())
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pm_info->secondary_startup = omap_secondary_startup_4460;
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pm_info->secondary_startup = omap4460_secondary_startup;
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else
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pm_info->secondary_startup = omap_secondary_startup;
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pm_info->secondary_startup = omap4_secondary_startup;
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pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
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if (!pm_info->pwrdm) {
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@ -352,6 +389,12 @@ int __init omap4_mpuss_init(void)
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save_l2x0_context();
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if (cpu_is_omap44xx()) {
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omap_pm_ops.finish_suspend = omap4_finish_suspend;
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omap_pm_ops.resume = omap4_cpu_resume;
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omap_pm_ops.scu_prepare = scu_pwrst_prepare;
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}
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return 0;
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}
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@ -87,7 +87,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
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/*
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* Update the AuxCoreBoot0 with boot state for secondary core.
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* omap_secondary_startup() routine will hold the secondary core till
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* omap4_secondary_startup() routine will hold the secondary core till
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* the AuxCoreBoot1 register is updated with cpu state
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* A barrier is added to ensure that write buffer is drained
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*/
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@ -200,7 +200,7 @@ static void __init omap4_smp_init_cpus(void)
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static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
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{
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void *startup_addr = omap_secondary_startup;
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void *startup_addr = omap4_secondary_startup;
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void __iomem *base = omap_get_wakeupgen_base();
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/*
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@ -211,7 +211,7 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
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scu_enable(scu_base);
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if (cpu_is_omap446x()) {
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startup_addr = omap_secondary_startup_4460;
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startup_addr = omap4460_secondary_startup;
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pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
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}
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@ -1,7 +1,7 @@
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/*
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* OMAP4 Power Management Routines
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* OMAP4+ Power Management Routines
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*
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* Copyright (C) 2010-2011 Texas Instruments, Inc.
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* Copyright (C) 2010-2013 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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@ -135,16 +135,16 @@ static void omap_default_idle(void)
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}
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/**
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* omap4_pm_init - Init routine for OMAP4 PM
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* omap4_init_static_deps - Add OMAP4 static dependencies
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*
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* Initializes all powerdomain and clockdomain target states
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* and all PRCM settings.
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* Add needed static clockdomain dependencies on OMAP4 devices.
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* Return: 0 on success or 'err' on failures
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*/
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int __init omap4_pm_init(void)
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static inline int omap4_init_static_deps(void)
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{
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int ret;
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struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
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struct clockdomain *ducati_clkdm, *l3_2_clkdm;
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int ret = 0;
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if (omap_rev() == OMAP4430_REV_ES1_0) {
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WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
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@ -163,7 +163,7 @@ int __init omap4_pm_init(void)
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ret = pwrdm_for_each(pwrdms_setup, NULL);
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if (ret) {
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pr_err("Failed to setup powerdomains\n");
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goto err2;
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return ret;
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}
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/*
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@ -171,6 +171,10 @@ int __init omap4_pm_init(void)
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* MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
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* expected. The hardware recommendation is to enable static
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* dependencies for these to avoid system lock ups or random crashes.
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* The L4 wakeup depedency is added to workaround the OCP sync hardware
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* BUG with 32K synctimer which lead to incorrect timer value read
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* from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
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* are part of L4 wakeup clockdomain.
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*/
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mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
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emif_clkdm = clkdm_lookup("l3_emif_clkdm");
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@ -179,7 +183,7 @@ int __init omap4_pm_init(void)
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ducati_clkdm = clkdm_lookup("ducati_clkdm");
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if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
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(!l3_2_clkdm) || (!ducati_clkdm))
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goto err2;
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return -EINVAL;
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ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
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ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
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@ -188,9 +192,42 @@ int __init omap4_pm_init(void)
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ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
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if (ret) {
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pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
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return -EINVAL;
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}
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return ret;
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}
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/**
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* omap4_pm_init - Init routine for OMAP4+ devices
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*
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* Initializes all powerdomain and clockdomain target states
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* and all PRCM settings.
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* Return: Returns the error code returned by called functions.
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*/
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int __init omap4_pm_init(void)
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{
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int ret = 0;
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if (omap_rev() == OMAP4430_REV_ES1_0) {
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WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
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return -ENODEV;
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}
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pr_info("Power Management for TI OMAP4+ devices.\n");
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ret = pwrdm_for_each(pwrdms_setup, NULL);
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if (ret) {
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pr_err("Failed to setup powerdomains.\n");
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goto err2;
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}
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if (cpu_is_omap44xx()) {
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ret = omap4_init_static_deps();
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if (ret)
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goto err2;
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}
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ret = omap4_mpuss_init();
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if (ret) {
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pr_err("Failed to initialise OMAP4 MPUSS\n");
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@ -206,7 +243,8 @@ int __init omap4_pm_init(void)
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/* Overwrite the default cpu_do_idle() */
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arm_pm_idle = omap_default_idle;
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omap4_idle_init();
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if (cpu_is_omap44xx())
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omap4_idle_init();
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err2:
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return ret;
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