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arc: Get rid of root core-frequency property 

Now when we switched to usage of real clk devices for CPU core
frequency those root properties make no sense any longer.
Se we're just getting rid of them here to not confuse readers of
our .dts files.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Christian Ruppert <christian.ruppert@alitech.com>
Cc: Noam Camus <noamca@mellanox.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Alexey Brodkin 2016-05-25 15:11:29 +03:00 committed by Vineet Gupta
parent 2547476a5e
commit 49acadff2a
15 changed files with 0 additions and 17 deletions
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2
arch/arc/boot/dts/abilis_tb100.dtsi
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@ -23,8 +23,6 @@
/ {
clock-frequency = <500000000>; /* 500 MHZ */
soc100 {
bus-frequency = <166666666>;

2
arch/arc/boot/dts/abilis_tb101.dtsi
View File

@ -23,8 +23,6 @@
/ {
clock-frequency = <500000000>; /* 500 MHZ */
soc100 {
bus-frequency = <166666666>;

1
arch/arc/boot/dts/axc001.dtsi
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@ -15,7 +15,6 @@
/ {
compatible = "snps,arc";
clock-frequency = <750000000>; /* 750 MHZ */
#address-cells = <1>;
#size-cells = <1>;

1
arch/arc/boot/dts/axc003.dtsi
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@ -14,7 +14,6 @@
/ {
compatible = "snps,arc";
clock-frequency = <90000000>;
#address-cells = <1>;
#size-cells = <1>;

1
arch/arc/boot/dts/axc003_idu.dtsi
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@ -14,7 +14,6 @@
/ {
compatible = "snps,arc";
clock-frequency = <90000000>;
#address-cells = <1>;
#size-cells = <1>;

1
arch/arc/boot/dts/eznps.dts
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@ -18,7 +18,6 @@
/ {
compatible = "ezchip,arc-nps";
clock-frequency = <83333333>; /* 83.333333 MHZ */
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;

1
arch/arc/boot/dts/nsim_700.dts
View File

@ -11,7 +11,6 @@
/ {
compatible = "snps,nsim";
clock-frequency = <80000000>; /* 80 MHZ */
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&core_intc>;

1
arch/arc/boot/dts/nsimosci.dts
View File

@ -11,7 +11,6 @@
/ {
compatible = "snps,nsimosci";
clock-frequency = <20000000>; /* 20 MHZ */
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&core_intc>;

1
arch/arc/boot/dts/nsimosci_hs.dts
View File

@ -11,7 +11,6 @@
/ {
compatible = "snps,nsimosci_hs";
clock-frequency = <20000000>; /* 20 MHZ */
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&core_intc>;

1
arch/arc/boot/dts/nsimosci_hs_idu.dts
View File

@ -11,7 +11,6 @@
/ {
compatible = "snps,nsimosci_hs";
clock-frequency = <5000000>; /* 5 MHZ */
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&core_intc>;

1
arch/arc/boot/dts/skeleton.dtsi
View File

@ -13,7 +13,6 @@
/ {
compatible = "snps,arc";
clock-frequency = <80000000>; /* 80 MHZ */
#address-cells = <1>;
#size-cells = <1>;
chosen { };

1
arch/arc/boot/dts/skeleton_hs.dtsi
View File

@ -8,7 +8,6 @@
/ {
compatible = "snps,arc";
clock-frequency = <80000000>; /* 80 MHZ */
#address-cells = <1>;
#size-cells = <1>;
chosen { };

1
arch/arc/boot/dts/skeleton_hs_idu.dtsi
View File

@ -8,7 +8,6 @@
/ {
compatible = "snps,arc";
clock-frequency = <80000000>; /* 80 MHZ */
#address-cells = <1>;
#size-cells = <1>;
chosen { };

1
arch/arc/boot/dts/vdk_axc003.dtsi
View File

@ -14,7 +14,6 @@
/ {
compatible = "snps,arc";
clock-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;

1
arch/arc/boot/dts/vdk_axc003_idu.dtsi
View File

@ -15,7 +15,6 @@
/ {
compatible = "snps,arc";
clock-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;