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drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv 

More .rodata string saving by avoid __I915__ magic inside WARNs.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Jani Nikula <jani.nikula@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
This commit is contained in:
Tvrtko Ursulin 2016-10-13 11:02:54 +01:00
parent 6e266956a5
commit 49cff963dd
7 changed files with 14 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/i915_drv.h
View File

@ -2859,7 +2859,7 @@ struct drm_i915_cmd_table {
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display) #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
/* DPF == dynamic parity feature */ /* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf) #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)

6
drivers/gpu/drm/i915/intel_color.c
View File

@ -273,7 +273,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
enum pipe pipe = intel_crtc->pipe; enum pipe pipe = intel_crtc->pipe;
int i; int i;
if (HAS_GMCH_DISPLAY(dev)) { if (HAS_GMCH_DISPLAY(dev_priv)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
assert_dsi_pll_enabled(dev_priv); assert_dsi_pll_enabled(dev_priv);
else else
@ -288,7 +288,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
(drm_color_lut_extract(lut[i].green, 8) << 8) | (drm_color_lut_extract(lut[i].green, 8) << 8) |
drm_color_lut_extract(lut[i].blue, 8); drm_color_lut_extract(lut[i].blue, 8);
if (HAS_GMCH_DISPLAY(dev)) if (HAS_GMCH_DISPLAY(dev_priv))
I915_WRITE(PALETTE(pipe, i), word); I915_WRITE(PALETTE(pipe, i), word);
else else
I915_WRITE(LGC_PALETTE(pipe, i), word); I915_WRITE(LGC_PALETTE(pipe, i), word);
@ -297,7 +297,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
for (i = 0; i < 256; i++) { for (i = 0; i < 256; i++) {
uint32_t word = (i << 16) | (i << 8) | i; uint32_t word = (i << 16) | (i << 8) | i;
if (HAS_GMCH_DISPLAY(dev)) if (HAS_GMCH_DISPLAY(dev_priv))
I915_WRITE(PALETTE(pipe, i), word); I915_WRITE(PALETTE(pipe, i), word);
else else
I915_WRITE(LGC_PALETTE(pipe, i), word); I915_WRITE(LGC_PALETTE(pipe, i), word);

8
drivers/gpu/drm/i915/intel_display.c
View File

@ -5034,7 +5034,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
* event which is after the vblank start event, so we need to have a * event which is after the vblank start event, so we need to have a
* wait-for-vblank between disabling the plane and the pipe. * wait-for-vblank between disabling the plane and the pipe.
*/ */
if (HAS_GMCH_DISPLAY(dev)) { if (HAS_GMCH_DISPLAY(dev_priv)) {
intel_set_memory_cxsr(dev_priv, false); intel_set_memory_cxsr(dev_priv, false);
dev_priv->wm.vlv.cxsr = false; dev_priv->wm.vlv.cxsr = false;
intel_wait_for_vblank(dev, pipe); intel_wait_for_vblank(dev, pipe);
@ -5099,7 +5099,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
intel_pre_disable_primary(&crtc->base); intel_pre_disable_primary(&crtc->base);
} }
if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) { if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
crtc->wm.cxsr_allowed = false; crtc->wm.cxsr_allowed = false;
/* /*
@ -10893,7 +10893,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
pos |= y << CURSOR_Y_SHIFT; pos |= y << CURSOR_Y_SHIFT;
/* ILK+ do this automagically */ /* ILK+ do this automagically */
if (HAS_GMCH_DISPLAY(dev) && if (HAS_GMCH_DISPLAY(dev_priv) &&
plane_state->base.rotation == DRM_ROTATE_180) { plane_state->base.rotation == DRM_ROTATE_180) {
base += (plane_state->base.crtc_h * base += (plane_state->base.crtc_h *
plane_state->base.crtc_w - 1) * 4; plane_state->base.crtc_w - 1) * 4;
@ -16591,7 +16591,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
if (crtc->active && !intel_crtc_has_encoders(crtc)) if (crtc->active && !intel_crtc_has_encoders(crtc))
intel_crtc_disable_noatomic(&crtc->base); intel_crtc_disable_noatomic(&crtc->base);
if (crtc->active || HAS_GMCH_DISPLAY(dev)) { if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
/* /*
* We start out with underrun reporting disabled to avoid races. * We start out with underrun reporting disabled to avoid races.
* For correct bookkeeping mark this on active crtcs. * For correct bookkeeping mark this on active crtcs.

2
drivers/gpu/drm/i915/intel_dp.c
View File

@ -1583,7 +1583,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
return ret; return ret;
} }
if (HAS_GMCH_DISPLAY(dev)) if (HAS_GMCH_DISPLAY(dev_priv))
intel_gmch_panel_fitting(intel_crtc, pipe_config, intel_gmch_panel_fitting(intel_crtc, pipe_config,
intel_connector->panel.fitting_mode); intel_connector->panel.fitting_mode);
else else

2
drivers/gpu/drm/i915/intel_dsi.c
View File

@ -1346,7 +1346,7 @@ static int intel_dsi_set_property(struct drm_connector *connector,
DRM_DEBUG_KMS("no scaling not supported\n"); DRM_DEBUG_KMS("no scaling not supported\n");
return -EINVAL; return -EINVAL;
} }
if (HAS_GMCH_DISPLAY(dev) && if (HAS_GMCH_DISPLAY(to_i915(dev)) &&
val == DRM_MODE_SCALE_CENTER) { val == DRM_MODE_SCALE_CENTER) {
DRM_DEBUG_KMS("centering not supported\n"); DRM_DEBUG_KMS("centering not supported\n");
return -EINVAL; return -EINVAL;

2
drivers/gpu/drm/i915/intel_fifo_underrun.c
View File

@ -254,7 +254,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
old = !intel_crtc->cpu_fifo_underrun_disabled; old = !intel_crtc->cpu_fifo_underrun_disabled;
intel_crtc->cpu_fifo_underrun_disabled = !enable; intel_crtc->cpu_fifo_underrun_disabled = !enable;
if (HAS_GMCH_DISPLAY(dev)) if (HAS_GMCH_DISPLAY(dev_priv))
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
else if (IS_GEN5(dev) || IS_GEN6(dev)) else if (IS_GEN5(dev) || IS_GEN6(dev))
ironlake_set_fifo_underrun_reporting(dev, pipe, enable); ironlake_set_fifo_underrun_reporting(dev, pipe, enable);

5
drivers/gpu/drm/i915/intel_hdmi.c
View File

@ -1265,6 +1265,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
{ {
struct intel_hdmi *hdmi = intel_attached_hdmi(connector); struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
struct drm_device *dev = intel_hdmi_to_dev(hdmi); struct drm_device *dev = intel_hdmi_to_dev(hdmi);
struct drm_i915_private *dev_priv = to_i915(dev);
enum drm_mode_status status; enum drm_mode_status status;
int clock; int clock;
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
@ -1287,7 +1288,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
status = hdmi_port_clock_valid(hdmi, clock, true); status = hdmi_port_clock_valid(hdmi, clock, true);
/* if we can't do 8bpc we may still be able to do 12bpc */ /* if we can't do 8bpc we may still be able to do 12bpc */
if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK)
status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
return status; return status;
@ -1297,7 +1298,7 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
{ {
struct drm_device *dev = crtc_state->base.crtc->dev; struct drm_device *dev = crtc_state->base.crtc->dev;
if (HAS_GMCH_DISPLAY(dev)) if (HAS_GMCH_DISPLAY(to_i915(dev)))
return false; return false;
/* /*