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mfd: cros ec: spi: Increase EC transaction delay 

50 us is not a long enough delay between EC transactions. At least 70 us
are needed for the 16 MHz STM32L part. Increase the delay to 200 us for
an extra safety margin.

Reviewed-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Derek Basehore 2013-11-18 11:30:48 +01:00 committed by Lee Jones
parent 9981a3146c
commit 49f91ac331
1 changed files with 4 additions and 3 deletions
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7
drivers/mfd/cros_ec_spi.c
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@ -50,10 +50,11 @@
/*
* Time between raising the SPI chip select (for the end of a
* transaction) and dropping it again (for the next transaction).
* If we go too fast, the EC will miss the transaction. It seems
* that 50us is enough with the 16MHz STM32 EC.
* If we go too fast, the EC will miss the transaction. We know that we
* need at least 70 us with the 16 MHz STM32 EC, so go with 200 us to be
* safe.
*/
#define EC_SPI_RECOVERY_TIME_NS (50 * 1000)
#define EC_SPI_RECOVERY_TIME_NS (200 * 1000)
/**
* struct cros_ec_spi - information about a SPI-connected EC